Monday, 2018-09-03

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cr1901_moderntinyfpga: Hrm, I wanted to do a USB IP in migen :/. I'm never going to get the opportunity to learn USB at this rate01:24
tinyfpgacr1901_modern: ill make sure to leave some bugs in there for you XD01:25
cr1901_modernis it going to be a CDC core written in pure migen?01:27
tinyfpgacr1901_modern: I think I will rewrite the whole thing in migen/litex01:27
xobstinyfpga: what are you looking for in terms of vexriscv-on-litex?  I find having an Etherbone bridge makes things oh-so-much easier, because debugging.01:28
tinyfpgacr1901_modern: I am going to focus on support for cpu-controlled USB core01:28
tinyfpgacr1901_modern: so it can be smaller and easier to use01:28
tinyfpgacr1901_modern: and I’m going to move most of it outside of the 48MHz clock’s impossible to meet timing on UP5K as it is today01:29
cr1901_modernhmmm... well tinyfpga soc can't run at 48MHz anyway01:30
cr1901_modernI'm probably going to set it to 32MHz01:30
cr1901_modernwhich'll be enough breathing room for now01:30
tinyfpgaxobs: I’m currently using the UART wishbone bridge, I don’t think I need vexriscv support until I’m ready to write a USB driver for the IP01:30
tinyfpgaxobs: I agree, the wishbone bridge is AWESOME01:30
tinyfpgaxobs: interactive python access to the wishbone fabric feels like I crawled inside the chip tron-style01:31
xobsI've not done much with the Python stuff.  But interactive GDB?  That's super sweet.01:32
tinyfpgaxobs: I’m just using the IPython REPL to read and write on the wishbone fabric01:34
tinyfpgaxobs: I’m going to add the Litescope next and eventually I’ll prototype some driver code in Python01:34
tinyfpgaxobs: will the vexrisc core support GDB and other debuggers?01:35
cr1901_moderntinyfpga: I may still do a USB CDC core in Migen on my own, but I'll make sure it doesn't conflict with your own goals. I really need to learn USB and starting at a spec isn't cutting it.01:35
xobstinyfpga: It uses openocd, which provides a gdb bridge.  So it'll support anything that speaks gdbserver.  Mostly gdb.01:36
tinyfpgacr1901_modern: I’ll try and keep the USB IP split into two halves so you could at least reuse the bottom half if desired01:36
cr1901_modernCool, I'll keep that in mind. Implementing the SIE/bitstuffing crap doesn't seem fun01:37
tinyfpgacr1901_modern: a CDC core in pure hardware is still nice since it could implement the wishbone bridge for CPU debugging01:37
tinyfpgaxobs: awesome01:37
xobsIf you end up making a USB-IP wishbone bridge (like the PCIe, UART, and Ethernet bridges), then the gdb will work seamlessly with the current setup.01:37
cr1901_modernxobs: Do you mean a serial port "USB" bridge, or a "CDC, but not actually a serial port" USB bridge? I would assume the latter wouldn't work seamlessly01:38
cr1901_modernUnless gdb can "talk to" USB without the need for CDC device class using its own mechanism01:38
xobscr1901_modern: I mean making a USB backend for litex_server.  Doesn't have to be CDC.  The vexriscv-openocd server speaks litex_server natively now.01:39
cr1901_modernxobs: So my issue w/ vexriscv-openocd is that it's very much out of date and I don't want to trudge through openocd source to merge HEAD into it01:40
cr1901_modernthe openocd ppl seem very set on a specific riscv debugging interface that vexriscv doesn't implement01:40
cr1901_modern(not to mention they are f***ing slow at accepting changes)01:40
cr1901_modernSo I think I'll have to sit out openocd support since I'm not willing to downgrade my "compiled-from-source version" :(01:41
xobsAgreed on that front.  The vexriscv approach of "jam stuff into the pipeline" is an interesting approach, and is completely different from the SiFive approach of "add more CSRs!"01:43
xobsAnd the world seems to follow SiFive.  They have a good marketing team.01:43
cr1901_modernriscv is funny... I have such mixed feelings about it. The privileged spec bites01:44
cr1901_modernI love the opcode encoding01:44
cr1901_modernI love no branch delay slots01:44
xobsStill, it's mostly just the "vexriscv.c" file.  The implementation we use kind of ignores the existence of jtag.  So it should be easyish to port to a new version.01:44
cr1901_modernI wish unaligned accesses were forbidden. I wish software walks were allowed.01:45
cr1901_modern(though I know why they did the former)01:45
cr1901_modernNot enough addressing modes01:45
cr1901_modernAnd embedded cores aren't even required to implement CSRs if they just implement the "E" extension01:46
xobsStill, having a debugger is important.  And with vexriscv and vexriscv-openocd, we at least have a debugger.01:52
xobsThe alternative, of course, being to use qemu for that.01:52
tinyfpgaxobs, cr1901_modern: I definitely want debugger support01:52
cr1901_modernI'm mostly complaining (what else is new?) that vexriscv-openocd is a fork, lacking features that I use, that is unlikely to be upstreamed01:53
tinyfpgaI just wonder if it’s possible to support debugging over a USB-IP that is also controlled by the CPU :/01:54
xobstinyfpga: That does seem challenging.  Especially since all the commands operate by setting the "halt" bit on the CPU.01:54
tinyfpgaxobs: if an ISR can run then it could work...but I’m not familiar with the vexriscv debug interface01:56
tinyfpgaxobs: do you have a pointer to the spec?01:56
xobsNope.  It literally halts the decoder, and works by jamming opcodes into the fetch stage.01:56
tinyfpgaxobs: gotchya01:56
xobsThe spec is super sparse.  Because it's mostly "write riscv instructions".
tpbTitle: GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation (at
tinyfpgacr1901_modern, xobs: maybe I can create a hybrid USB mode...CPU retains ultimate control, but can setup an hardware-autonomous path for data to be processed by another IP02:03
tinyfpgacr1901_modern, xobs: then the CPU could transfer control to hardware for specific endpoints.  You could implement two USB CDC interfaces: one is controlled directly by the CPU, the other one bypasses the CPU controller data buffers and goes to a hardware block02:07
tinyfpgacr1901_modern, xobs: that other hardware block could be a wishbone bridge...that should enable debug, Litescope, and wishbone access, right?02:07
cr1901_modernHmmm that would be interesting... idk how much extra space it would take for 2 interfaces (plus multiplexing to one PHY)02:08
tinyfpgacr1901_modern: I believe it would still be smaller than the current fully hardware USB design02:09
tinyfpgacr1901_modern: it’s a little bit of extra state and data muxing, but not too bad02:10
cr1901_modernI don't see how the second interface solves the problem of "the CPU is in use while you're debugging it" unless it's full hardware02:11
tinyfpgacr1901_modern: the hardware accelerated pathway completely bypasses the CPU02:12
tinyfpgacr1901_modern: once you have the endpoints configured and set up, you don’t need much from the just need it to pull data out of the buffer and tell the USP core that it’s ready for more data02:13
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tinyfpgacr1901_modern: for the hardware accelerated path the data will go to a seperate buffer controlled by hardware along with some logic to tell the USB core when it’s ready for more data02:14
tinyfpgacr1901_modern: the accelerated endpoints won’t need any CPU intervention to function02:14
cr1901_modernthen how is that different from a fully hardware design :)?02:14
tinyfpgacr1901_modern: the fully hardware design has to implement the control endpoint in hardware, which is a pain02:15
tinyfpgacr1901_modern: today, it also tries to be efficient with blockram by using a total of two blockrams for all the endpoints combined02:15
tinyfpgacr1901_modern: and then it does some other magic to ping-pong buffers02:15
tinyfpgacr1901_modern: I dread touching that code...this will be a much more efficient and reusable solution02:16
cr1901_modernOkay I think I'm done w/ the technical stuff tonight02:16
futarisIRCcloudtinyfpga: Sounds like some good ideas for the USB core.02:21
tinyfpgafutarisIRCcloud: hopefully I’ll get it working tomorrow :)02:23
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futarisIRCcloudtinyfpga: Cool. I guess you're targeting Lattice first? Any plans to get it working on Xilinx Series 7 later?02:30
tinyfpgafutarisIRCcloud: it should “just work” on other FPGAs02:31
tinyfpgafutarisIRCcloud: current bootloader already works on ICE40, ECP5, and Xilinx Series 702:32
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CarlFKrohitksingh_wor1: hi!04:15
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rohitksingh_workCarlFK: hi!04:17
CarlFKrohitksingh:  did you know the numato usb relay suffers something similar to the hdmi2usb?04:17
CarlFKnot exactly the same - I paste in a bunch of chars, only 1/2 get echoed back, but the commands still execute as if all of them were received.04:18
rohitksingh_workCarlFK: err, sorry. I've no idea on the relays front since it is handled by separate team. I'm not familiar with their working and their firmware. Maybe you could send a mail to [email protected] which will create a support ticket? Then, I can talk with the relevant guys regarding this issue.04:21
CarlFKrohitksingh_work: meh.  it still works, it is just visually a little alarming04:21
CarlFKreally I was hoping you had insight to solving the hdmi2usb problem :p04:22
CarlFKif it would be like the relay board, that would be much better04:22
rohitksingh_workCarlFK: oh, no idea on the hdmi2usb issue either :/04:26
CarlFKrohitksingh_work: we have a few workarounds - so no biggie.04:27
tpbTitle: Having the serial port open prevents video from streaming · Issue #14 · timvideos/HDMI2USB-fx2-firmware · GitHub (at
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rohitksingh_workCarlFK: Okay. The issue linked above seems to be a different bug than uart echo one.04:31
CarlFKyeah - I was just hoping there was something similar.  having to use workarounds makes me grumpy :p04:31
rohitksingh_workCarlFK: yup, these kind of workarounds (for example, in the linked issue above) are terrifying :o04:33
CarlFKlol = yes.04:33
CarlFKim bummed that there isn't a unix filter to throttle stdio04:34
rohitksingh_workwill this kind of solution work ?04:40
tpbTitle: How to rate-limit a pipe under linux? - Super User (at
xobsCarlFK: what about throttle(1)? Either way, it sounds like the implementation needs CTS and RTS implemented. Or a bigger FIFO...04:47
CarlFKSee throttle --help for more information04:56
CarlFKthrottle: unknown option --help04:56
CarlFKbut.. why didn't anyone find this 2 years ago?04:56
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CarlFK"would agree with this, but there doesn't seem to be a standard package for Ubuntu"  right.  I had to use a snap on cosmic (beta)  so it may be this new05:01
rohitksingh_worksigh...there was already a throttle utility all this time.05:24
CarlFKdoh.  yes.  2003-01-18   Initial Release05:43
CarlFKI was hoping it was like 6 months ago :p05:43
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cr1901_modernmithro: Perhaps we should have an Altera board just to exercise that LiteX functionality? (Future idea)06:56
tpbTitle: GitHub - vpecanins/max1000-tutorial: Tutorial and example projects for the Arrow MAX1000 FPGA board (at
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futarisIRCcloudHmmm. ~8k LUTs on a 40 AUD Intel MAX1000...07:09
cr1901_modernfutarisIRCcloud: Well it's more than enough to hold a CPU07:13
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cr1901_moderntinyfpga: Is there a possible ETA for when the "-n"/"name" option will be implemented? I am in fact blocked on it07:36
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tinyfpgacr1901_modern: ok, I can do that today13:52
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Shari2Hi. I have problems with bring up of my new numato opsis. Pattern to output 0 is working. Input 0 (rock64 sbc) to Output0 is not working. Any suggestions how to debug this?15:49
CarlFKShari2: hi there16:02
CarlFKShari2: status command - what is the input 0 line?  should look like these:16:04
CarlFKinput0:  0x0 (@0.00 MHz) (disabled)16:04
CarlFKinput1:  1280x720 (@74.25 MHz) (capturing)16:04
Shari2input0:  0x0 (@112.21 MHz) (capturing)16:05
CarlFKoh wait .. first q should always be: do you have a magic cable?16:06
Shari2no. what is a magic cable?16:06
Shari2i have this one 1162-06C,
tpbTitle: HDMI High Speed with Ethernet Male-Male Cables -- DataPro (at
CarlFKthe "magic" is a little active amplifier in  the end of the cable16:10
CarlFKwhich makes it directional - ends are labeled "source" and "TV"  and it wont work if you plug it in backwards16:11
Shari2passive cables wont work?16:12
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CarlFKNote: 75ft and 100ft lengths use bus-powered active boosters.   While they require no external power, this does make the cable  directional, as indicated by "Input" and "Output" labels on the cable  heads.16:12
CarlFKa passive cable can work if the source is "good"16:13
CarlFKbut we have found that so many sources are not good, that we just use the active cable all the time.16:13
CarlFKbrb - need to make coffee16:15
Shari2is the numato opsis a "good" source? can i loop output 0 to input 0?16:16
CarlFKlooks like no:  I just hooked 0 to 0,  input0:  0x0 (@74.25 MHz) (capturing)16:30
Shari2i got "input0:  1280x720 (@74.25 MHz) (capturing)" now after reboot of the rock6416:34
Shari2and its gone ...16:34
Shari2will try active cable16:34
Shari2thank you16:34
CarlFKsure thing16:35
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Shari2the ddr line of the status command is always empty. I there a problem with the ddr?16:38
CarlFKhmm, not sure I have ever noticed that before ... mithro ^^^16:46
Shari2input0:  1280x720 (@74.25 MHz) (capturing) input1:  0x0 (@0.00 MHz) (disabled) output0: [email protected] from input0 (underflows: 0) output1: off EDID primary mode:   [email protected] EDID secondary mode: [email protected] encoder: 1280x720 @ 0fps from input0 (q: 85) ddr:16:47
CarlFKyeah - I have that too.16:50
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Shari2"encoder: 1280x720 @ 28fps from input0 (q: 85)". VLC only has a orange/yellow bar running left to right and back. Any suggestions?17:05
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Shari2dmesg has some uvc messages "uvcvideo 1- Entity type for entity Camera 1 was not initialized!"17:34
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cr1901_moderntinyfpga: Cool thanks. Additionally, I got tinyfpga to boot a 32MHz lm32 softcore w/ 10kB of RAM and 2kB of cache17:49
tinyfpgacr1901_modern: awesome!17:49
tinyfpgacr1901_modern: I am excited to try it out17:49
cr1901_modernI had to forcefully override the icetime step; nextpnr crashes on this design for some reason, and icetime claims the design doesn't pass timing (it works fine)17:50
mithrocr1901_modern: cool!17:55
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mithrocr1901_modern: is this with or without the multipliers?17:55
cr1901_modernmithro: with17:55
mithroShari2: hi!17:55
mithrocr1901_modern: what's the resource usage like?17:56
mithroI'll be around in about an hour17:56
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Shari2mithro: Hi.17:56
cr1901_modernblock RAM is nearly gone, plenty of breathing room wrt logic cells17:56
cr1901_modernlike 3000 logic cells left over17:56
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tpbTitle: voctomix-outcasts/ at master · CarlFK/voctomix-outcasts · GitHub (at
CarlFKShari2: ah, i bet you hit another gotcha: disconnect from the serial console, connect to the video stream, then connect to the serial console again.  you can do both, but you need to connect the video first.18:03
Shari2CarlFK:  will try18:04
Shari2CarlFK: the car is gone, but still no video18:08
Shari2CarlFK: the bar*18:09
CarlFKShari2: what firmware version?  (version will show lots, look for   git describe: v0.0.4-277-g2b3ff0418:09
Shari2CarlFK:  git describe: v0.0.4-194-ge14edee18:10
CarlFKShari2: no idea if it will help, but I've been working with that ver and it is passing all my tests18:10
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Shari2CarlFK: "gst-launch-1.0 v4l2src device=/dev/video0 ! jpegdec ! queue ! videoconvert" throws gstjpegdec.c(1394): gst_jpeg_dec_handle_frame (): /GstPipeline:pipeline0/GstJpegDec:jpegdec0: Decode error #55: Not a JPEG file: starts with 0x97 0x9718:20
Shari2CarlFK: will try your version18:20
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Shari2CarlFK: with version  v0.0.4-277-g2b3ff04,  gst-launch throws "gstjpegdec.c(1394): gst_jpeg_dec_handle_frame (): /GstPipeline:pipeline0/GstJpegDec:jpegdec0: Decode error #9: Bogus Huffman table definition", vlc behavior not changed18:42
Shari2CarlFK: input0:  1280x720 (@74.25 MHz) (capturing) input1:  0x0 (@0.00 MHz) (disabled) output0: [email protected] from input0 (underflows: 0) output1: off EDID primary mode:   [email protected] EDID secondary mode: [email protected] encoder: 1280x720 @ 0fps from input0 (q: 85) ddr:18:43
CarlFKShari2: try this:
tpbTitle: Ubuntu Pastebin (at
CarlFKand to make sure the serial connection problem is really fixed: sudo rmmod uvcvideo && sudo modprobe uvcvideo18:46
Shari2CarlFK: /GstPipeline:pipeline0/GstJpegDec:jpegdec0: No valid frames decoded before end of stream, gstvideodecoder.c(1161): gst_video_decoder_sink_event_default (): /GstPipeline:pipeline0/GstJpegDec:jpegdec0:18:48
Shari2CarlFK: do i need to have output 0 connected?18:48
CarlFKno - but I would use the pattern as a source18:48
Shari2CarlFK: with manual usb reconnect, ERROR: from element /GstPipeline:pipeline0/GstV4l2Src:v4l2src0: Device '/dev/video0' failed during initialization Additional debug info: gstv4l2object.c(3722): gst_v4l2_object_set_format_full (): /GstPipeline:pipeline0/GstV4l2Src:v4l2src0: Call to S_FMT failed for MJPG @ 1280x720: Input/output error Execution ended after 0:00:05.10094313718:59
Shari2CarlFK: dmesg, uvcvideo: Failed to set UVC probe control : -110 (exp. 26).19:00
CarlFKShari2: rmmod/modprobe/dmesg:
tpbTitle: Ubuntu Pastebin (at
CarlFKlet me power cycle the Opsis and get you that dmesg19:03
Shari2CarlFK: with powercycle + rmmod/modprobe i get the same output19:05
CarlFKhmm, tornado and flood warning... um.. leme go make sure all my wndows are closed ..19:07
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mithroI'm here now19:33
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CarlFKShari2: im back19:35
CarlFKShari2: you have the right /dev/video device right?  laptops have webcams that show up as video019:36
mithroCarlFK: bunnie did a lot of work to improve the HDMI performance on the NeTV2, at some point we should backport his stuff to the Opsis and hopefully it'll improve performance there too19:36
Shari2CarlFK: im on a desktop PC without any webcam. video0 is gone with opsis disconnected19:37
CarlFKShari2: what distro?19:38
CarlFK(shouldn't matter, just wondering)19:38
Shari2CarlFK: ubuntu bionic19:38
CarlFKhandy - that's what my opsis is hocked up to too.19:38
Shari2CarlFK: i see non empty isochronous transfer with wireshark, maybe the issue is in the host stack19:39
Shari2CarlFK: can i disable encoding to see raw pixel data?19:42
mithroShari2: sadly not19:44
mithrotinyfpga: Is that last tweet sigrok?19:45
tinyfpgamithro: it’s sigrok, but using my external LA19:45
mithrotinyfpga: Ahh19:45
tpbTitle: Support pulseview / sigrok directly · Issue #8 · enjoy-digital/litescope · GitHub (at
mithrotinyfpga: And
tpbTitle: litescope/ at master · enjoy-digital/litescope · GitHub (at
mithroxobs: Do we have a good C Etherbone library now?19:46
CarlFKShari2: im almost bak.. need to heat up some coffee20:00
CarlFKShari2: im back.  let me bounce my opsis and paste syslog20:17
Shari2CarlFK: wb20:17
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CarlFKmithro: can you give me a number of seconds to wait between power off and on?20:45
mithroShari2: btw, where in the world are you?20:49
Shari2mithro: germany20:49
mithroShari2: Did you get one of the C3VOC Opsis boards?20:49
Shari2mithro: not that i know20:50
Shari2mithro:  i got my board from
tpbTitle: Sinelec Technologies (at
mithroShari2: wow, that is random20:51
cr1901_modernmithro: Do you still keep in touch w/ the person who runs upy proper? If so, are there any talks about uniting fupy w/ upy?20:54
mithrocr1901_modern: Yes and Yes20:54
* cr1901_modern is glad to hear20:54
cr1901_modernI don't really want to, but I may cut back the RAM on tinyfpga to 8kB, so there's extra bram for user hardware a user may wish to attach20:55
cr1901_modern31/32 brams used if I use 10kB20:56
mithrocr1901_modern: So, when you going to send me a pull request?20:56
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cr1901_modernmithro: Blocked on updating litex currently, which is blocked on t1nyfpga (don't want to bother him :P) and me fixing vexriscv-Verilog20:57
mithrocr1901_modern: Well, lm32 first right?20:57
cr1901_modernIf you don't mind multiple PRs (one to add lm32 lite, another to fix vexriscv), sure20:58
mithrocr1901_modern: Yes, please try to send lots of small PRs rather than one huge one :-)20:58
CarlFKShari2: power off on dmesg
tpbTitle: Ubuntu Pastebin (at
Shari2CarlFK: same here21:02
CarlFKmithro: any suggestions on what repo/wiki to stash stuff like this?  (like dmesg when opsis powers on)21:05
CarlFKI guess it can go with  "common problems"21:06
CarlFKmithro: um..  is now just 2 404 links21:11
tpbTitle: HDMI2USB-litex-firmware/ at master · timvideos/HDMI2USB-litex-firmware · GitHub (at
CarlFKShari2: im guessing you have been poking around and have some tabs open - see anything that looks like a good place for my dmesg dumps and such?21:12
Shari2CarlFK: no idea21:12
mithroSorry, got distracted21:18
mithroCarlFK: maybe ?21:19
tpbTitle: Common Errors · timvideos/litex-buildenv Wiki · GitHub (at
CarlFK mithro - sounds good.  thanks.21:20
mithroCarlFK: or maybe
tpbTitle: Numato Opsis · timvideos/litex-buildenv Wiki · GitHub (at
mithroCarlFK: Could you look at cleaning up too?21:20
tpbTitle: Digilent Atlys · timvideos/litex-buildenv Wiki · GitHub (at
mithroCarlFK: I think we should have a "How to use an Opsis for conference recording" type page?21:22
CarlFKmithro: I think that can be
tpbTitle: Adding an Opsis Machine DebConf Videoteam Ansible documentation (at
CarlFKmithro:   there could be more to it than that.. but ... low priority21:24
tpbTitle: HowTo Presentation Recording · timvideos/litex-buildenv Wiki · GitHub (at
tpbTitle: HowTo Presentation Recording · timvideos/litex-buildenv Wiki · GitHub (at
mithroYou now have TODOs :-P21:26
CarlFKmithro: the Opsis should all be on the DC docs, and i'm not gonna put anything for Atlys until someone says they are going to use one.21:28
mithroCarlFK: Do you have a flashing document somewhere?21:29
CarlFKmithro: so not sure if thsoe TODOs help21:29
CarlFKmithro: yes - it is linked from
CarlFK(which is easy to remember and how I always find it)21:30
mithroCarlFK: I'm thinking we should close down that wiki?21:30
mithroCarlFK: I've removed a bunch of obsolete stuff from that repo21:31
mithroCarlFK: And moved other stuff which is still relevant to the LiteX-BuildEnv wiki...21:31
CarlFKmithro: as long as you find a new *wiki* for that page to live on21:31
CarlFKit is gotten pretty static, but I am sure I will bump into things that need to be updated21:32
CarlFKmithro: like this still isn't solid:  firmware version: Stable/testing/custom21:33
CarlFKShari2: I haven't forgotten about you21:33
Shari2CarlFK: i test other stuff, no worry21:34
mithroShari2: It must be pretty late in germany at the moment?21:35
CarlFKonly 30 till midnight :p21:35
Shari2mithro: yep21:35
mithroShari2: Is your interest mainly doing recording of user groups / conferences or doing FPGA video hardware development?21:36
Shari2mithro: FPGA stuff in general21:36
mithroShari2: Okay cool, then you should probably think about joining this channel with a proper IRC client rather than webchat -- it's a great place to get help with FPGA stuff and the Opsis stuff21:37
Shari2mithro: any suggestion for linux irc client? never used irc much21:39
mithroShari2: I use IRCCloud21:40
CarlFKShari2: use matrix ;)21:42
CarlFKShari2: mostly because there are nice android matrix clients, and the irc bridge works good enough.21:43 is the android matrix client I use.  it works good enough I haven't considered looking for something else.21:44
mithroShari2: I'm trying to make the wiki at the best place to get started with the toolchain we use for the HDMI2USB firmware21:46
tpbTitle: Home · timvideos/litex-buildenv Wiki · GitHub (at
mithroShari2: still a WIP21:46
mithroShari2: It also supports
tpbTitle: Welcome to FPGA MicroPython (FμPy) | (at
CarlFKmithro: what is the hardware conf you are going to soon?21:47
mithroBe back in 30 minutes, going to find some lunch21:48
mithroNo free lunch in the office on a public holiday :-/21:53
Shari2I am off to sleep. Bye.22:46
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CarlFKwow, it's been an hour?22:47
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cr1901_modern_florent_: FYI whenever you decide to upgrade libcompiler_rt... the riscv subdirectory under builtins now provides a "mulsi3.c" (not that there's anything wrong w/ the one you provide)23:51
mithroCarlFK: where has this day gone :-(23:55
CarlFKmithro: no kidding.23:59
mithroI have a project I was going to get you to get ps1 to do for me :-P23:59

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