Sunday, 2018-09-02

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mithroCarlFK: The wiki at is probably going away sometime soonish00:40
tpbTitle: Home · timvideos/HDMI2USB Wiki · GitHub (at
mithroCarlFK: I think you might care about or ?00:41
tpbTitle: Flashing Firmware · timvideos/HDMI2USB Wiki · GitHub (at
CarlFKmithro: the flashing page is used pretty often , so it needs to live somewhere00:42
mithroCarlFK: I've cleaned out a lot of the rest of that page00:42
cr1901_moderntinyfpga: wishbone slave is the normal way00:42
mithroCarlFK: Which one are you using?00:42
tpbTitle: Flashing Firmware · timvideos/HDMI2USB Wiki · GitHub (at
tinyfpgamithro: I want to instantiate a specific RAM module00:43
mithrotinyfpga: You mean a specific RAM black box?00:43
tinyfpgamithro: I almost have it working....implementing a wb slave like cr1901_modern suggestes00:43
tinyfpgamithro: correct00:44
mithroCarlFK: Shall we delete the other?00:44
CarlFKmithro: yes00:44
mithroCarlFK: done00:45
CarlFKmithro: as long as you are looking at that page, maybe you know if I can do this: check box that hides/unhide sections - but I think I need .js - like any of the [x]ShowMore tic boxes here:
tpbTitle: veyepar: Welcome to CircuitPython! (at
cr1901_moderntinyfpga: If you are using litex you also need to make a call to add_memory_region for wishbone-based devices to show up in your C defines00:49
cr1901_modernOr you can call register_mem which will add the FPGA connections _and_ create the C defines00:51
tinyfpgacr1901_modern: I’m using register_mem01:03
cr1901_modernHow many FPGA devs does it take to debug a single board?01:05
mithroWell, the README at should now make a lot more sense...01:23
tpbTitle: GitHub - timvideos/litex-buildenv: An environment for building LiteX based FPGA designs. Makes it easy to get everything you need! (at
mithroLooks like conda is down :-(01:32
xobstinyfpga: I just woke up, but did you get your litex stuff working?01:39
tinyfpgaxobs: working through it, I just got some custom SRAM black boxes working on the wishbone bus01:42
cr1901_modernIf you get an lm32 working with spiflash on tinyfpga on your first try, I'm going to eat my mattress01:42
xobsI have a super barebones first draft attempt at a ws2812b spec catcher.  It uses the PLL, and is at'01:43
tinyfpgacr1901_modern: I’m just using the UART wishbone bridge for now01:43
tinyfpgaxobs: I get a 404 when I try to access that page01:43
xobsIt also uses my lxbuildenv environment.  But that might be less interesting if you've already got everything set up.01:43
xobs (no trailing apostrophe?)01:44
tpbTitle: ws2812b-catcher/ at master · xobs/ws2812b-catcher · GitHub (at
tinyfpgacr1901_modern: what SPI core are you using to get memory-mapped SPI access?01:44
xobsThe pll values come from the output of "icepll"01:44
tinyfpgaxobs: nice...but why do you call it “Spec Catcher”?01:45
tinyfpgaxobs: I’m not familiar with that term01:45
tinyfpgacr1901_modern: so I should be able to put that on the wishbone bus as a slave and access it over the UART bridge, I might just give that a try next01:46
cr1901_modernSure, that'll work.01:46
xobstinyfpga: It's the start of a project.  We received a batch of ws2812b chips from the manufacturer that would output an out-of-spec signal even when you fed an in-spec signal in.  The idea was to use a ws2812b to sweep good signals in and make sure good timing signals come out.01:46
cr1901_modernThe problem w/ my generated SoCs based on traces is: PC and branch control gets corrupted01:47
mithroAnyone used
tpbTitle: direnv - unclutter your .profile (at
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cr1901_modernNah, I just manually update all my .profiles01:54
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cr1901_modernthough I'm prob gonna start using a .bash_aliases file soon01:55
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cr1901_modernmithro: I think the "minimal" lm32 variant should be altered to have: multiplier/divider/multishift disabled. And a "lite" variant is "the current min, except with 2kB icache". Would you object if I made those changes?02:03
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mithrocr1901_modern: Nope02:03
cr1901_modernCool, thanks02:03
cr1901_modernAnd this will finally let me get rid of those awful hacks I have in my fork of tinyfpga-soc02:04
mithrocr1901_modern: Did you ever see ?02:04
tpbTitle: WIP - Make CPUs more configurable by mithro · Pull Request #2 · mithro/litex · GitHub (at
cr1901_modernI have not, will take a look02:04
cr1901_moderntinyfpga: If you've seen _florent_'s tinyfpga-soc, I'll be uploading mine soon. Mine is technically a fork, but has significantly diverged from _florent_'s while I test/break stuff02:05
cr1901_modernSo you may wish to clone it/treat it as a totally separate repo :)02:05
mithrocr1901_modern: The aim with that pull request was to do proper CPU configurations02:05
mithrocr1901_modern: I was trying to put together a minimal or1k at that time too I think....02:06
cr1901_modernOh I do think I remember this PR02:06
cr1901_modernwhat is the @property decorator?02:07
cr1901_modernxobs: Is vexriscv still borked due to the bad underscore in the filename?02:08
tpbTitle: Python @property: How to Use it and Why? - Programiz (at
tinyfpgacr1901_modern: ok, I’m using that same soc for the start of another project, so it should be at least a little familiar to me02:13
xobscr1901_modern: Yeah.  You can prove that by doing:  wget ''; yosys -p 'read_verilog VexRiscv-MinDebug.v' > /dev/null02:14
cr1901_moderntinyfpga: Cool. I like lm32 b/c internally it's easy to read and not written in "FP wrapper over Verilog" lang :P02:25
cr1901_modernxobs: Alright, I'll test this. Phew... gonna be a busy few hours02:26
tinyfpgacr1901_modern: so i integrated the SPI flash core into my soc02:28
tinyfpgacr1901_modern: and I’m using the bridge to read data off of SPI flash02:28
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tinyfpgacr1901_modern: I’m reading from address zero02:28
tinyfpgacr1901_modern: and the data I receive does not match what I expect to get02:29
cr1901_modernmithro: My opinion re: pull #2 in Litex is "let's sort out the current hardcoded min/lite/normal variants we have right now, which should be fine for most use cases, and revisit adding custom configs on top of the hardcoded variants using pull #2."02:29
cr1901_moderntinyfpga: "icesleep -s"?02:29
tinyfpgacr1901_modern: icepack -s02:29
tpbTitle: MiSoC / LiteX "CPU Configs" - Google Docs (at
mithrocr1901_modern: - I listed a bunch of "CPU Configs" I thought should exist in that doc02:30
tpbTitle: MiSoC / LiteX "CPU Configs" - Google Docs (at
* mithro goes to move that into the LiteX BuildEnv wiki02:31
cr1901_moderntinyfpga: Yes, that. Hmmm...02:31
tinyfpgacr1901_modern: im wondering if this is related to your issue02:31
tinyfpgacr1901_modern: I’m going to investigate further02:31
cr1901_moderntinyfpga: Well, it's possible I didn't test this02:32
cr1901_modernAlthough I'm pretty sure I did at some point02:32
cr1901_moderntinyfpga: In any case, I welcome alternate approaches to debugging that I didn't think of, even if they should've been obvious in retrospect02:33
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cr1901_modernI was mainly focusing on what came _out_ of the SPI flash, not what the CPU "sees"02:33
tinyfpgacr1901_modern: what value are you passing into SpiFlash for “dummy”?02:34
cr1901_modernthe default02:34
tinyfpgacr1901_modern: I believe it should be “8”, the default is way off02:34
cr1901_modernIf you try it and it works, I'll send you a photo of me eating my mattress02:35
tinyfpgacr1901_modern: i set it to 8 just now and the data matches what I expected to see02:35
tinyfpgacr1901_modern: that parameter is the number of dummy bits between the SPI command+address and the beginning of the data02:35
cr1901_modernBut the traces I saw show the correct data come out of the chip02:36
tinyfpgacr1901_modern: it’s 8 SPI clocks on the Adesto parts (and most SPI flash chips as far as I know)02:36
tinyfpgacr1901_modern: the correct data will still come out of the chip, but the SpiFlash core will interpret it incorrectly02:36
* cr1901_modern believes you, just trying to parse it02:37
cr1901_modernmithro: Re:, I think you showed me this doc a few days ago?02:37
cr1901_modernI prefer the current terminology "lite", "min", and ""02:38
tinyfpgacr1901_modern: that parameter just tells the core how many clocks to wait before shifting in the data, the default waits 15 clocks so it will drop the first 7 bits of actual data02:38
cr1901_modernwhere "" is default and "full"02:38
tinyfpgacr1901_modern: you can just post the photo here when you’re ready XD02:38
cr1901_modernMy God... and I missed that all the time02:38
cr1901_modernmithro: where "" is default and corresponds to what I would call "full", i.e. "Performance" on your chart.02:40
cr1901_modernBut this is a bikeshed we can talk about in a bit02:40
cr1901_modernI'm going to test now and see what happens02:42
cr1901_moderntinyfpga: For the record, it is still possible for me to crash tinyfpga w/ lm32 without spiflash, but only w/ arachne-pnr and only with certain I/O removed02:50
cr1901_modernthe same design w/ nextpnr succeeds, so it could be arachne weirdness02:50
cr1901_moderntinyfpga: it worked02:57
cr1901_modernI owe you a photo02:57
cr1901_modernNext time I strip my bed I'll take it02:57
tinyfpgacr1901_modern: woohoo!!02:59
mithrocr1901_modern: What was the problem in the end?03:03
cr1901_modernmithro: dummy in the SPIFlash core wasn't set properly03:04
mithrocr1901_modern: Oh03:04
cr1901_modernmithro: So you and tinyfpga were right all along- the SPIflash core was badly configured. I didn't think to check the boundary between the SPIflash and CPU03:05
mithrocr1901_modern: Hrm? I would have thought to try reading the spiflash data using the wishbone bridge?03:05
cr1901_modernmithro: Because I saw LA traces that showed the correct data coming into the chip, I didn't think to attach a wishbone bridge.03:06
cr1901_modernI figured that something was going wrong inside the CPU and swapping it out for a bridge wouldn't tell me anything03:07
cr1901_moderncc: daveshah... this probably means that spiflash boot will work on your 5k board too03:11
cr1901_modernThe BIOS works as well03:21
mithroCarlFK: - The build is slowly looking more green03:24
CarlFKmithro: yay.  that's a lot of red  still03:25
mithroCarlFK: Your build matrix was set to allow the failure of jobs 1112.25, 1112.26, and 1112.27.03:25
mithroCarlFK: so, only one which is causing issues is 1112.2103:26
mithroCarlFK: It should also no longer be blocking the hdmi2usb builds03:26
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cr1901_moderntinyfpga: How does the "-i" switch to tinyprog work?03:44
cr1901_modernDoes it match against the "name" JSON entry?03:44
cr1901_modernor the UUID?03:44
tinyfpgacr1901_modern: it uses the uuid, you only need to use the first few characters03:45
cr1901_modernIs there any way to tell tinyfpga to program based on name (in case you have multiple boards that are tinyprog compatible attached)?03:46
tinyfpgacr1901_modern: not the idea to batch program multiple boards at once?03:47
cr1901_modernNo... the idea is that "tinyprog should be considered a generic programmer class in Migen/LiteX, but we need a way to tie the programmer to a specific board each time we construct an instance"03:50
cr1901_modernso a "tinyprog" class instance meant for say, Arty, doesn't accidentally try looking for (or programming!) a BX board03:50
cr1901_moderntinyfpga ^^03:52
tinyfpgacr1901_modern: I see, yes, that’s an option I can add04:00
tinyfpgacr1901_modern: maybe -t/—type or -n/—name04:01
tinyfpgacr1901_modern: file an issue on the TinyFPGA-Bootloader repo04:01
tpbTitle: Images · timvideos/litex-buildenv Wiki · GitHub (at
tpbTitle: Add `name` option to `tinyprog` · Issue #20 · tinyfpga/TinyFPGA-Bootloader · GitHub (at
benreynwarmithro: I've had a look at cocotb in the past, but have been put off by the fact that the standard way to write a test involves Makefiles.  What is timvideos using for unit testing?04:38
mithrobenreynwar: I like that you think we have unit testing :-P04:38
benreynwarmithro: Ha!04:38
mithrobenreynwar: Our testing is CarlFK :-P04:39
CarlFKI have a test!04:40
CarlFKI wrote 3 maybe.  not sure 2 of them really work.  but I got Jenkins to run one. once.04:40
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benreynwarmithro: Gonna watch your video now.  Cheers for the link.04:53
CarlFKmithro:  Platform: opsis                 Target: hdmi2usb (default: video)05:14
CarlFKit built - does it get pushed to right away, or wait for all the flavors to build ?05:14
tpbTitle: GitHub - timvideos/HDMI2USB-firmware-prebuilt: Prebuilt firmware for the HDMI2USB devices (such as the Numato Opsis and the Digilent Atlys board) and OS drivers. (at
CarlFKmithro: never mind - I found v0.0.4-277-g2b3ff04 2 hours ago - I'll try that05:17
CarlFKmithro: if I have the right udev rules, should this need sudo?  sudo hdmi2usb-mode-switch -v --mode serial05:23
mithroCarlFK: no, it should not05:34
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mithroCarlFK: assuming your in the right groups....05:35
CarlFKmithro: good news - test pattern:
CarlFKmithro: what group do I need?  im in: juser dialout sudo audio video plugdev05:37
mithroCarlFK: they look right...05:39
CarlFKmithro: k - I'll try again in a bit without sudo and see what happens05:40
cr1901_modernxobs: Just checked. This is a yosys error I think05:51
cr1901_modernerr s/error/bug/05:52
cr1901_modernIt should accept "-" in filenames05:52
xobs<freenode_cr1 "xobs: Just checked. This is a yo"> cr1901_modern: is that a valid verilog module name, though? It's not like C, where module names are [a-zA-Z0-9]?05:53
cr1901_modernOh... right05:53
cr1901_modernerr... dunno :P05:53
xobsIf you keep the filename the same but just change the module name, it works.05:54
cr1901_modernyes looks like you're correct, whoops05:54
CarlFKmithro: more good news:
cr1901_modernxobs: Yea, my change royally broke LiteX too, I'm fixing it now05:58
CarlFKmithro: ^^ test rig is working again.  helps to plug the pi's hdmi into the Opsis :p05:58
CarlFKmithro: more goodness: on the pi: [email protected]:~ $ sudo fbi --vt 1 1280x720_input.png - captured:
cr1901_modernxobs: See gitter. I don't think I'm solving this tonight unless Dolu1990 gets back to me real fast06:12
xobsNo hurry. It's easy enough to rename it.06:13
mithroHrm, apparently you can't have a C++ compiler without a C std library...06:15
mithrohey xobs06:26
mithrohow are things in Singapore?06:26
CarlFKmithro: somewhere are some test pattern images.  or code to generate them.  any idea where?06:32
tpbTitle: GitHub - timvideos/test-patterns: Test patterns for debugging video problems. (at
mithroThat was my first guess06:35
CarlFKgood guess :p06:35
mithroCarlFK: I feel like I need a "swear jar" type thing where you put coin into everytime you ask me about something you should have guess....06:37
cr1901_modern"I'm not gonna swear, but I am going to KICK THIS DOGHOUSE DOWN!!"06:38
xobsmithro: Singapore is warm like usual. I'm starting over on the coriolis stuff. I found out its not dead, just that work continued on a branch I didn't know about...06:40
mithroxobs: Damn06:40
xobsIt's not a total loss - at least it's not dead! And now I know more about its internals than I otherwise would have.06:40
mithroxobs: Finally booked my OrConf trip06:45
xobsOh excellent. When do you get there?06:45
mithro2pm the 20th06:46
xobsNeat. I get there at 8am the day before.06:47
tpbTitle: FuPy - Adding new board HowTo - Google Docs (at
cr1901_modernLast edit August 13, 2017. Has it really been that long already ._.?06:59
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mithrotinyfpga: how did you go in the end?07:24
tinyfpgamithro: i have custom RAM blocks working, I got the SPI core working with correct data, and I implemented a simple pulse density modulation core for use as a DAC and/or LED control07:29
tinyfpgamithro: learned a lot about litex/migen07:29
tinyfpgamithro: I think my next step is pulling in USB components07:30
tinyfpgamithro: and adapting them for litex...I have some ideas now that I know how it works07:30
mithrotinyfpga: would be good to upload your tests so we can see how your going07:31
tinyfpgamithro: I’m still using the UART wishbone bridge, I was having trouble getting arachnepnr to successfully route the soc with lm32 enabled07:32
mithrotinyfpga: there are a bunch of patterns / antipatterns that you pick up from _florent_07:32
mithrotinyfpga: cr1901_modern has some suggestions for a better "minimal" lm32 config07:32
tinyfpgamithro: yeah, I just followed the TinyFPGA SoC I’m sure there are things that can be changed07:33
tinyfpgamithro: once i have my USB core working and a CPU core is ready, I’ll be moving to an embedded CPU core for most work07:33
mithrotinyfpga: _florent_ threw that together at CCC if I recall correctly07:33
mithroStill very much a WIP07:34
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_florent_mithro: yes the idea was just to have a first version working. The minimal config is for another usage (code in rom), we could think about the best variants to create and i'm open to changing that08:58
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shorneCarlFK: mithro:  I am basically the maintainer for qemu, I am happy to support the litex configuration.  I know we will be using it.  Let me know when you are ready for upstreaming and I can review before we send the patches upstream.11:54
shorneI am a bit busy for the next two weeks though.  I am between jobs and have to study for some kind of certification test before I start the next job.11:55
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tinyfpga_florent_: this is my first time using litex/migen and I am _really_ liking it15:50
CarlFKtumbleweed: The repository ' cosmic Release' does not have a Release file.16:11
tpbTitle: Index of /timvideos/fpga-support/ubuntu (at
tumbleweedCarlFK: copied to cosmic. Wait for the publisher to come round16:34
CarlFKtumbleweed: thanks again - hope you can tollerate the slow dribble of discovery16:34
CarlFKtumbleweed: shorne: i'm curious - any idea why "apt build-dep qemu" ends with update-initramfs: Generating /boot/initrd.img-4.17.0-9-generic16:35
tumbleweedCarlFK: because of an indirect dependency on e2fsprogs and xfsprogs16:46
CarlFKok, I can kinda accept that.16:47
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_florent_tinyfpga: great :)17:12
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CarlFKshorne: do you remember this from about 8 moths ago I think:   util/memfd.c:40:12: error: static declaration of ‘memfd_create’
tpbTitle: Ubuntu Pastebin (at
CarlFKI found some accepted patches, manually fixed up the 4 or 5 in  but ran into another fail that was similar: I found talk about it, but couldn't find patches.17:20
tpbTitle: GitHub - timvideos/qemu-litex (at
CarlFKI'm trying to figure out how to get it to build so we can consider upstreaming17:22
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CarlFKmithro:     should/can I re-run just this one:  The job exceeded the maximum time limit for jobs, and has been terminated.19:42
mithro_florent_: did you see I started collecting a lot of the LiteX related docs here ->
tpbTitle: Home · timvideos/litex-buildenv Wiki · GitHub (at
mithrotinyfpga: would love to get feedback, it's always interesting to see new people who have had other experiences try LiteX20:27
tinyfpgamithro: yeah, I will be providing feedback and massaging the soc example for florent21:00
tinyfpgamithro: I want to make it easy for people to use and understand so they can extend it21:01
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tinyfpgaxobs, cr1901_modern, mithro: what’s needed for vexriscv to work well in litex?22:19
tinyfpgaonce I have my USB IP implemented and working for litex I want to get it running with a soft core22:19
CarlFKtinyfpga: do you know about the usb problems with htmi2usb?22:51
tinyfpgaCarlFK: nope, not familiar with those problems22:52
CarlFK1 - send chars too fast, most get lost (queue overflow?)22:52
CarlFK2 - connect to the serial interface first (/dev/ttyACM0) that somehow screws up /dev/video022:53
tinyfpgaCarlFK: I’m working with the USB IP from the TinyFPGA Bootloader22:53
CarlFKbut connect to /dev/video0 first and all is well22:53
CarlFKwell... if you are becomeing a usb expert.. please looookkkkk!!!!22:53
tinyfpgaCarlFK: both the video device and serial device are over usb?22:53
CarlFKI'm only an expert at whining about it :p22:54
CarlFKvideo is like a usb webcam22:54
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CarlFKmithro: can I close issues I opened?  like
tpbTitle: usb stream broken · Issue #431 · timvideos/HDMI2USB-litex-firmware · GitHub (at
CarlFKseems to be fixed.23:30
tpbTitle: Having the serial port open prevents video from streaming · Issue #14 · timvideos/HDMI2USB-fx2-firmware · GitHub (at
CarlFKmithro: another I think can be closed - this one you opened:
tpbTitle: Support resetting an video input without resetting the output · Issue #80 · timvideos/HDMI2USB-litex-firmware · GitHub (at

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