Saturday, 2018-09-01

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CarlFKmithro: doesn't build on 18.04 lts00:05
tpbTitle: GitHub - timvideos/qemu-litex (at
mithroYes I think it needs to be rebased00:05
CarlFKcan the changes you/someone made be upstreamed?00:16
CarlFKmithro: ^^ hoping I can get a qemu hacker to work it all out.00:16
mithroCarlFK: That would take a lot of time00:19
tpbTitle: Branches · mithro/qemu · GitHub (at
mithroCarlFK: Have to chat with shorne to get a better idea of what of my stuff has already gone upstream - I don't think much00:21
mithroCarlFK: There might be some stuff here too ->
tpbTitle: Branches · mithro/qemu-litex · GitHub (at
mithroshorne: Do you know if these changes were merged upstream?
tpbTitle: Branches · mithro/qemu · GitHub (at
mithroCarlFK: No idea what the status of those branches is either00:23
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* mithro is going to head home and continue doing the documentation update from there...01:00
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shornemithro: for qemu patches.  I dont think the litex hardware description was.14:16
shornethe evbar changes were (to allow different memory maps)14:16
shorneI think the cpucfg one was14:17
shornePlease let me know if you want to get all that stuff upstream we can work on a plan.  I know there are kernel patches too for the evbar support14:18
CarlFKshorne: re qemu - my guess is he would like all of it upstream, but do the qemu devs see enough value in it to maintain the additional code forever ?14:48
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mithroHey shorne15:56
mithrocr1901_modern: Did you have any luck yesterday?15:56
mithroshorne: Any chance your still around?15:58
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mithroHrm, is it HowTo or Howto ?16:22
CarlFKlol - "It is common practice to write the phrase as "HOWTO" in the open-source community"
tpbTitle: How-to - Wikipedia (at
CarlFK" As of 2009 A Google search for "How To" results in a comprehensive list of HowTo sites."16:26
CarlFK HowTo - given nowhere do I see Howto16:27
cr1901_modernmithro: No, and I took a break from it yesterday soon after b/c it was irritating me16:28
mithroCarlFK: I started moving the Google Doc for LCA2018 FPGA Miniconf to
tpbTitle: HowTo LCA2018 FPGA Miniconf · timvideos/litex-buildenv Wiki · GitHub (at
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mithroxobs: Do you have thoughts on Zephyr verse ChibiOS?16:38
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CarlFKmithro: the irc link doesn't get me into #linux.conf.au16:44
mithroCarlFK: You mean the webchat thingy?16:44
CarlFKmithro: and because of the freenode spam, cfk2 == Cannot send to channel: #timvideos16:45
CarlFKmithro:  yes.16:45
mithroCarlFK: okay16:45
mithroCarlFK: The aim is to eventually split the FPGA Miniconf page out into sections16:46
CarlFKmithro:  im guessing you can drop the #lca bit16:46
mithroYeah, possibly16:46
mithroOne of the things I did like about the Google Doc was how easy it was for people to suggest changes...16:48
CarlFKtumbleweed: if you are around, can you bump the PPA stuff for cosmic?16:48
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mithroCarlFK: I started splitting out the udev rules into their own repo ->
tpbTitle: GitHub - timvideos/litex-buildenv-udev: udev rules for LiteX BuildEnv supported boards (at
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CarlFKmithro: nice - i17:08
mithroCarlFK: I was ponder if we should split the HDMI2USB udev rules from the FPGA dev board rules or not...17:09
CarlFKmithro: nice - i'm still fuzzy on how to diagnose what is going on, like if some other udev rule is interfering17:09
mithroCarlFK: I don't trust your machine if you are still using the ppas...17:10
CarlFKmithro: keep hdmi2usb and dev stuff  together.17:11
CarlFK"the ppas" is a little vague .  I seem to remember a command, probably udevadm, that would show as rules fired.. know what I am talking about?   or should I dig into my firewire history of years ago...17:16
mithro maybe?17:17
tpbTitle: GitHub - timvideos/litex-buildenv-udev: udev rules for LiteX BuildEnv supported boards (at
CarlFKmithro: here we go (should have skimmed man first)  udevadm monitor -  Listens to the kernel uevents and events sent out by a udev rule and        prints the devpath of the event to the console.17:18
CarlFKmithro: power cycling the opsis:
tpbTitle: Ubuntu Pastebin (at
mithroCarlFK: That looks all good17:24
CarlFKmithro: yay.  any idea what (media) is about?  KERNEL[815216.554497] add      /devices/pci0000:00/0000:00:1c.7/0000:07:00.0/usb3/3-1/3-1:1.0/media9 (media)17:24
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mithroUDEV  [815216.579193] add      /devices/pci0000:00/0000:00:1c.7/0000:07:00.0/usb3/3-1/3-1:1.2/tty/ttyACM0 (tty)17:28
mithroUDEV  [815216.581634] add      /devices/pci0000:00/0000:00:1c.7/0000:07:00.0/usb3/3-1/3-1:1.0/video4linux/video0 (video4linux)17:28
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mithrolunch time for me!19:58
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CarlFKsynaption[m]: are you expecting me at ps1 today?20:00
CarlFKmithro: I have one of these
tumbleweedCarlFK: I am around now20:06
CarlFKplugged in a usb cable, dmesg/syslog/lsusb doesn't show anything.20:06
CarlFKtumbleweed: super low priority, but would be handy if the PPAs worked with cosmic20:07
CarlFKtumbleweed:  like right now I am trying to see if a with a newer kernel solves something like this problem:
tpbTitle: [net,v3] r8169:fix "rtl_counters_cond == 1 (loop: 1000, delay: 10)" log spam. - Patchwork (at
CarlFKbecause:  [email protected]:~/bin$ dmesg |wc  ->    2046   22506  18618620:13
CarlFK[email protected]:~/bin$ dmesg |grep -v rtl_counters_cond |wc  ->       0       0       020:13
tumbleweedCarlFK: which PPA?20:13
CarlFKit eats all my dmesg !!20:13
CarlFKum.. whatever ansible used :p20:14
CarlFKsec.. I think I can find the error20:14
CarlFKtumbleweed: ' cosmic Release' does not have a Release file.\n20:16
tpbTitle: Index of /timvideos/voctomix/ubuntu (at
tumbleweedCarlFK: copied. It'll take half an hour to publish, probably20:24
CarlFKtumbleweed: thank you!20:24
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CarlFKhey... where is my image?!20:50
* CarlFK[m] uploaded an image: 20180901_152356.jpg (800KB) < >20:50
tinyfpgamithro: how do I use the PLL in litex?20:52
mithrotinyfpga: Your PLL is just a primitive you instantiate directly, right?20:53
tinyfpgamithro: is there a standard way to do it fornice40+litex or should instantiate the PLL module myself?20:53
tinyfpgamithro: ok, so litex doesn’t do anything special for PLLs then20:53
mithrotinyfpga: Not at the moment20:54
mithrotinyfpga: See ?20:54
tpbTitle: litex-buildenv/ at master · timvideos/litex-buildenv · GitHub (at
tinyfpgamithro: next question, how do I use the UARTWishboneBridge?20:54
tinyfpgamithro: i enabled it in my soc, but now I want to talk to the soc from my host computer20:54
mithrotinyfpga: You'll probably want multiple clock domains20:54
tinyfpgamithro: yes, ultimately I will want multiple clock domains, but I’m trying to get up on my feet first20:55
tinyfpgamithro: I’m not at all familiar with litex/migen20:55
mithrotinyfpga: Basically you start the litex_server using something like "litex_server uart [port] [baudrate]"20:57
mithrotinyfpga: Then you can connected to it using a python console20:58
mithrotinyfpga: I use this script ->
tpbTitle: litex-buildenv/ at master · timvideos/litex-buildenv · GitHub (at
mithrotinyfpga: the litex-buildenv tests/ will auto start the required proxy for uart/pcie21:02
tpbTitle: litex-buildenv/ at master · timvideos/litex-buildenv · GitHub (at
mithrotinyfpga: It's all based around etherbone....21:04
tinyfpgamithro: ok, I’m working on getting litex on Windows so can access the serial port21:06
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mithrotinyfpga: _florent_ and cr1901_modern use Windows a bit21:07
* CarlFK[m] uploaded an image: 20180901_160329.jpg (769KB) < >21:09
mithroCarlFK: O21:10
mithroCarlFK: I'm pretty sure we wouldn't be able to get those parts21:10
CarlFKmithro: really hoping to be able to just buy the unit and flash new custom firmware21:11
CarlFKlast chip coming up...21:11
mithroCarlFK: I highly doubt it21:12
* CarlFK[m] uploaded an image: 20180901_160517.jpg (786KB) < >21:12
CarlFKrats.  It is a nice size for a test pattern generator21:12
tpbTitle: Home Theater Video Processors - Lattice Semiconductor (at
CarlFKmithro: it has a  "USB port for performing a system software update."21:14
mithroCarlFK: Nothing you posted so far as firmware in it...21:16
mithroCarlFK: Just image encoder / decoder...21:16
CarlFKmithro: there's a heat sink over a chip. guessing thats an fpga21:17
tinyfpgamithro: what’s the “common” package in the script?21:17
CarlFKmy guess is kinda based on "well everything these days is an fpga, and what else could be updated over usb?"21:17
mithroCarlFK: It's like just a management SoC21:18
mithroCarlFK: Probably something like
tpbTitle: Home Theater Video Processors - Lattice Semiconductor (at
tinyfpgamithro: nm, I found the rest of the project :)21:19
mithrotinyfpga: the are just some quick tools for getting some useful probing tools21:21
CarlFKmithro: well, the good news is I can power it with a usb battery and it will spit out a 720p black with a green "no signal" box that floats around.   so ... kinda lets me see if a projector is working.21:25
tinyfpgamithro: ok, so now it’s complaining about csr.csv....I’m assuming that’s the config register map? I don’t see this being generated as part of the litex build of TinyFPGA SoC21:26
mithrotinyfpga: Yeah21:26
tpbTitle: litex-buildenv/ at master · timvideos/litex-buildenv · GitHub (at
tpbTitle: litex-buildenv/ at master · timvideos/litex-buildenv · GitHub (at
tinyfpgamithro: ok, thanks21:28
mithrotinyfpga: Things are still a bit of a mess - I'm hoping that we can clean some of it up with the lxbe-tool stuff21:30
mithrotinyfpga: going to get coffee be back later..21:37
mithrotinyfpga: you might be better of doing most of your dev on the arty and then switching afterwards - having tftp boot firmware and wishbone over Ethernet is really nice21:44
tinyfpgamithro: I already have the UART wishbone bridge connected and a programmer connected to the board21:46
tinyfpgamithro: this will help me learn migen/litex better21:46
tinyfpgamithro: by the way, how do I instantiate a Verilog module from migen/litex? Looking for examples I don’t see much21:47
mithroIt's all about the csrs21:47
mithroUnless it's timing critical, move it into firmware21:47
tinyfpgamithro: agreed, but I need to instantiate the PLL21:48
tinyfpgamithro: then I will instantiate the front-end of the USB hardware21:49
mithrocr1901_modern: probably has an ice40 example of PLL in Migen somewhere...21:49
tinyfpgamithro: I’m pretty happy to move as much as possible to software21:49
mithroYeah, C is so much easier to write :-)21:50
tinyfpgamithro: I just need an example or documentation of any Verilog module being instantiate in migen/litex21:50
tinyfpgamithro: maybe florents USB3 test does that...21:50
tpbTitle: LiteX for Hardware Engineers · timvideos/litex-buildenv Wiki · GitHub (at
tinyfpgamithro: thanks!!21:53
tinyfpgacr1901_modern: awesome! :) I’ll be using this....21:55
cr1901_moderntinyfpga: I did this elsewhere in the project I yanked this from, but you'll also want: "m.clock_domains.cd_sys = ClockDomain()"21:56
tinyfpgamithro, cr1901_modern: ok, I can now read and write the FPGA blockram from my computer XD22:17
mithrotinyfpga: \o/22:17
mithrotinyfpga: Good first step22:17
tinyfpgamithro: it’s starting to make more sense22:18
tinyfpgamithro: being able to access the soc from my computer is fantastic22:18
mithrotinyfpga: It is :-P22:18
mithrotinyfpga: The problem is you quickly get use to it....22:18
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mithrocr1901_modern: Thoughts on ?22:38
tpbTitle: Targets · timvideos/litex-buildenv Wiki · GitHub (at
cr1901_modernPerhaps base should be split into "base" (as described) and "base-lite" (using SPIflash for ROM, internal blockram for SDRAM)?22:43
mithrocr1901_modern: Hrm - that is almost min with the addition of spiflash?22:44
cr1901_modernI actually see it more as "base with the detriment of spiflash", b/c spiflash execution is still usable for things you'd expect from a base system like micropython22:45
cr1901_modernfor instance, tinyfpga will make a good upy system, but only if it can execute from spiflash. But it'll never get targets more complex than that (no offense tinyfpga :P)22:46
mithrocr1901_modern: Is there any reason you /wouldn't/ want external ram?22:47
tinyfpgacr1901_modern: hey, maybe the _BX_ won’t get much more complex XD22:47
cr1901_modernmithro: If the board doesn't come with one...22:47
mithrocr1901_modern: Then it's not in base.py22:47
tinyfpgacr1901_modern: you can have external SPI SRAM22:48
cr1901_modernahhh, nevermind then22:48
* mithro changes the wording to "on board memory interfaces"22:48
mithroI guess you could have a hyperram pmod...22:48
cr1901_modernSure, but let's cross that bridge later. you clarified my confusion22:49
mithrocr1901_modern: But that shouldn't be part of the "base" config22:49
cr1901_modernThat's fine then22:49
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tpbTitle: Environment Options · timvideos/litex-buildenv Wiki · GitHub (at
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tinyfpgacr1901_modern: do you know how to implement a custom Memory to be added to the wishbone interconnect in litex?23:28
tinyfpgacr1901_modern: or do you know of any examples?23:28
tinyfpgacr1901_modern: maybe the best option is to just implement it as a wb slave23:30
mithrotinyfpga: BTW If you don't say my name I won't necessarily see your request :-)23:33
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at
mithrotinyfpga: These are probably the lines you want ->
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at
CarlFKmithro: is there a text file of23:40
CarlFKmithro: is there a text file of firmware build results?    so I can find other opsis-hdmi2usb to try23:41
tinyfpgamithro: yeah, I found I need to make my own version of SRAM23:42
mithroCarlFK: what do you mean?23:42
mithrotinyfpga: What do you mean?23:42
mithrotinyfpga: You should be able to just import that wishbone.SRAM module and add another?23:43
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CarlFKmithro: I want to try other firmware builds, but I am not sure how to find successful builds - I can use but I may hit the github limit23:44
mithrobenreynwar: We have been hacking on litex-buildenv here most of the day23:44
mithrobenreynwar: tinyfpga has been learning migen23:44
mithroCarlFK: Did we move to github pages based stuff?23:45
benreynwarmithro: Cool.  I saw that you were involved in litex.23:45
tpbTitle: GitHub - timvideos/HDMI2USB-firmware-prebuilt at gh-pages (at
CarlFKmithro: I remember talking about it.  that's all I remember.23:46
mithrobenreynwar: I'm probably the biggest FOSS user outside of _florent_23:46
mithroCarlFK: I forget where then end up getting published23:46
benreynwarmithro:  I looked at migen a couple of years ago, but decided I needed to be conservative and stick to VHDL.  I'm kind of regretting it now!23:46
mithrobenreynwar: What are you doing again?23:46
mithrobenreynwar: I made the same decision along while back - have you seen my talk about it?23:47
mithroCarlFK: They end up here ->
benreynwarmithro: At work I do LPDC error correction cores.23:48
benreynwarmithro: Haven't seen your talk.  Where's it at?23:48
benreynwarLow density parity check.  It's an error correction algorithm.23:48
CarlFKmithro: is there a list of all the builds?23:48
mithrobenreynwar: BTW You should look at cocotb it your intested in better verilog testing...23:48
benreynwarmithro: Got to take the kids to the park now, but will likely be back on this evening.23:49
mithroCarlFK: even sorted for you in the right way...23:49
mithroCarlFK: You probably won't hit github limits with those URLs..23:51
CarlFKmithro: revs.txt is the only one that looks like it might have what I want,   any idea what it represents?23:52
mithroCarlFK: it's a listing of the directories under archive23:53
tpbTitle: HDMI2USB-firmware-prebuilt/opsis/hdmi2usb/lm32 at gh-pages · timvideos/HDMI2USB-firmware-prebuilt · GitHub (at
CarlFKmithro: like I want opsis-htmi2usb.. hmm. so I still have to dig into each dir and see if there is an image file23:54
mithroCarlFK: Yes, but much quicker to do it23:56
mithroCarlFK: We could generate a full index if you want I guess...23:56
tpbTitle: HDMI2USB-litex-firmware/ at master · timvideos/HDMI2USB-litex-firmware · GitHub (at
mithrobenreynwar: I'll probably still be here23:58

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