Thursday, 2018-08-23

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CarlFKwhat tool is used for schematic design?00:45
CarlFKkicad.  never mind.00:46
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tpbTitle: Add VexRISCV configuration suitable for iCE40 sized devices · Issue #2 · m-labs/VexRiscv-verilog · GitHub (at
cr1901_modernmithro: I generated such a config, I'm trying to test it now... (like literally now)01:29
cr1901_modernI'll be up for a few hours still, since sleep is elusive during normal sleep hours it seems01:30
mithrocr1901_modern: We are about to start hacking on FuPy01:30
mithrocr1901_modern: Can you comment on that issue01:30
cr1901_modernmithro: done01:33
mithrocr1901_modern: Thanks!01:34
cr1901_modernI _really_ wish I saw the blurb about the d-cache bus earlier though01:34
cr1901_modernIt's a waste of resources on ice40 to have a d-cache01:35
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tpbTitle: FuPy on iCE40 - Google Docs (at
mithroewen: and
tpbTitle: Add VexRISCV configuration suitable for iCE40 sized devices · Issue #2 · m-labs/VexRiscv-verilog · GitHub (at
mithrocr1901_modern: You were having issues with the lm32 on the ice40, right?01:51
cr1901_modernmithro: Yes. I'm taking an old repo for that and adding a vexriscv branch01:56
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CarlFKmithro: whats the fupy url?02:44
cr1901_modernWhy does my tinyfpga soc keep rese- oh, the pin dedicated to reset is floating02:46
cr1901_modernthat would be a good reason02:46
* CarlFK[m] uploaded an image: VectorImage_2018-08-22_094415.jpg (332KB) < >02:49
CarlFKfpga-ing here too02:49
CarlFKsorta :p02:50
cr1901_modern_florent_: Could you take a look at my two PRs to litex when convenient? They are quality-of-life changes, but really helpful03:14
mithrocr1901_modern: Merged03:22
cr1901_modernmithro: Thanks :P. Didn't know you have commit access to litex now03:24
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tpbTitle: FPGA MicroPython (FuPy) · GitHub (at
cr1901_modernI'm guessing not, but is Dolu1990 ever on IRC?03:58
* cr1901_modern doesn't actually know scala, big shock03:58
mithroewen: It should be here ->
tpbTitle: Home · timvideos/litex-buildenv Wiki · GitHub (at
mithroewen: But it is not :-P04:09
mithroewen: I think "export CPU=vexriscv" ?04:09
mithrocr1901_modern: Could you help ewen get started with vexriscv on an arty?04:10
mithroewen: Maybe CPU=picorv32 ?04:10
cr1901_modernewen: "export BOARD=arty TARGET=base CPU=picorv32 HDMI2USB_ENV=1" should be enough to set your environment, then run "make"04:12
mithroewen: => SiFive GNU Embedded Toolchain04:15
mithroewen: Maybe?04:15
mithroewen: Or
tpbTitle: GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation (at
cr1901_modernmithro: I would use the insns posted by clifford on picorv32 repo04:16
cr1901_modernI've compiled it successfully on Windows w/ minor tweaks to (texinfo BS causes building docs to fail, and makeinfo can't be disabled during a gcc build)04:17
cr1901_modernmithro: Sleep is about to take hold. I'm out tomorrow, but I should be here during the night04:35
mithrocr1901_modern: Okay04:41
tpbTitle: WIP: Adding tinyfpga and RISC-V support by mithro · Pull Request #34 · timvideos/litex-buildenv · GitHub (at
tinyfpgamithro: anything for me to try out there?04:45
mithrotinyfpga: Not yet04:45
mithroCarlFK: Did you end up solving that lm32 LC error assertion thingy?04:49
mithroCarlFK: We finally ran into that here!04:49
CarlFKmithro: nope  Aeva said "it looks like gcc has a different libs path"04:50
CarlFKmithro: but.. older OSs (like stuff from last year) don't have the problem04:51
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mithroexport LANG=/usr/lib/locale/C.UTF-8/05:23
tpbTitle: debian - loadlocale.c _nl_intern_locale_data assertion error - Unix & Linux Stack Exchange (at
mithroCarlFK: That should gix the problem?05:23
mithroI think the LANG should be something like $CONDA_DIR/share/locale or something...05:32
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ewenmithro: now exists, with some vague information on supported soft CPUs05:52
tpbTitle: SoftCPUs · timvideos/litex-buildenv Wiki · GitHub (at
mithroewen: So I was thinking we should move towards using crosstool-ng for building the crosscompilers as that is what conda uses internally ->
tpbTitle: GitHub - mithro/conda-hdmi2usb-packages at crosstool-ng (at
tpbTitle: litex-buildenv/ at master · timvideos/litex-buildenv · GitHub (at
tpbTitle: GitHub - mithro/lxbe-tool: LiteX Build Environment tool. (at
CarlFKmithro: yay!06:19
CarlFKmithro: oh, missed the ? .. did it fix it?06:20
CarlFKgoing shopping bye  - good luck!06:22
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mithroxobs: You had vexrisc-v debugging via network working at some point right?06:55
xobsmithro: That's the only method I've gotten working.  Eventually I'll need to add JTAG debugging for other reasons.06:56
tpbTitle: Debugging · timvideos/litex-buildenv Wiki · GitHub (at
mithroxobs: At some point I'd like to try the JTAG debugging via something using MuraxSoC style?06:56
xobsThat seems more like how the vexriscv people intended it to work.  As opposed to gluing it to Wishbone like I did.06:58
mithroxobs: Did you have any more thoughts on my lxbe-tool stuff?06:58
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mithroxobs: It is likely I'll be doing recruiting for developing that over the next couple of days07:12
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tpbTitle: Snippet | IRCCloud (at
mithro SoC BIOS / CPU: VexRiscv / 100MHz07:19
ewenmithro: Yay!  So CPU=vexriscv and CPU=picorv32 seem to work to build BIOS.  Currently CPU=picorv32 seems to be more challenging to build micropython...07:24
xobsmithro: The fundamental problem you're trying to solve is "How much do I trust the end-user's environment?" and answers range from "Not at all" (which results in a VM or Docker solution) to "Quite a bit" (which is what does).  Conda is somewhere in the middle, tending towards "Not at all".07:26
ewenmithro: The crt0 assembly that I can't build, due to missing include, is copied out of litex: third_party/litex/litex/soc/software/libbase/crt0-picorv32.S07:29
mithroxobs: Yes - the idea with the tool was to have "providers" which means that we can share all the common parts while still having different ideas on how much we trust stuff07:29
xobsmithro: I do like that notion.07:30
ewenmithro: the vexriscv (crt0-vexriscv.S) one is *much* simpler, with no includes07:30
ewenI'll try building with CPU=vexriscv instead07:30
mithroxobs: Like we all have to deal with the issues around bloody submodules07:30
mithroxobs: And installing python modules into the environment07:30
mithroxobs: And checking the versions of things....07:31
mithroxobs: etc07:32
mithroxobs: Setting things like PYTHONHASHSEED and similar too :-P07:32
xobsDistro development is hard.07:32
mithroxobs: Yeah07:34
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mithroewen -- FYI: - This uses the minimal variant of LM32 that is now integrated in LiteX. - I tested it on B2, but someone else tested it on BX successfully.07:47
tpbTitle: GitHub - enjoy-digital/tinyfpga-soc: TinyFPGA SoC based on LiteX (at
xobsmithro: Oh, you were talking earlier about dcache/icache for vexriscv.  What brought that on, and what did you end up doing?07:48
xobsI noticed Wishbone is hooked up through those caches.  Is it possible to hook it up a different way?07:48
mithroxobs: Looks like it was fixed here ->
tpbTitle: Possible problem with DCACHE when using VexRiscv · Issue #85 · enjoy-digital/litex · GitHub (at
mithroFYI - Hi _florent_!07:50
mithro_florent_: We will be hacking on FuPy for the next ~5-6 days07:53
_florent_cool, what are your goals for these 5-6 days?07:54
xobsmithro: I see, that addresses a cache bug that vexriscv had.  When I briefly tried it I was having trouble building a vexriscv core with a smaller cache.  Is it possible to have a 0-byte cache?  Or, rather, what's the smallest cache that's possible while still having Wishbone support?07:58
mithroxobs: oh, that is a different issue08:05
mithro_florent_: get tinyfpga support into LiteX-BuildEnv and get micropython stuff upstream08:06
tpbTitle: Add VexRISCV configuration suitable for iCE40 sized devices · Issue #2 · m-labs/VexRiscv-verilog · GitHub (at
mithroxobs: Talks about no cache configurations there08:08
tpbTitle: Include files from litex. by mithro · Pull Request #15 · fupy/micropython · GitHub (at
mithro_florent_: We have Nick Zoic who is a MicroPython maintainer here...08:11
mithroand will probably talk to other micropython people tomorrow...08:11
_florent_mithro: ok interesting!08:12
_florent_for tinyfpga support into LiteX-BuildEnv, you will probably need to run the firmware directly  (without the bios), or run code from the flash08:14
mithro_florent_: Yeah - similar to how the MimasV2 works08:27
_florent_ok good, i wasn't aware you were already doing that on MimasV208:28
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futarisIRCcloudmithro: Is everyone that is working on micropython for  tinyfpga in Sydney for PyCon AU 2018?09:08
futarisIRCcloudAnd which tinyfpga(s) are you targeting?09:09
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mithrofutarisIRCcloud: yes09:41
mithrofutarisIRCcloud: welcome remote contributors!09:41
mithrofutarisIRCcloud: tinyfpga-bx09:41
mithrofutarisIRCcloud: probably tinyfpga-b2 as well probably because I have one...09:42
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futarisIRCcloudmithro: BX. Shame it's out of stock on little bird / sparkfun Australia.
mithrofutarisIRCcloud: I could put one in the mail for you....09:45
mithroOr tinyfpga could :-P09:45
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futarisIRCcloudCool. I'm really looking forward to the EX series with Type-C USB.09:47
mithroSo am I10:17
daveshahWe all are :D10:19
daveshahVery happy with my prototype10:19
daveshahWould like to see the CC lines connected though10:20
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tpbTitle: Standard Cells, open source (at
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xobsmithro: thanks!13:30
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felix_hmm, i wonder if it is easily possible to formally verify a design written in litex/migen directly in python without having to poke the generated verilog code17:59
mithroxobs: Seems up your alley :-P20:21
tinyfpgadaveshah: maybe I can pull the CC pins out to testpoints on the bottom, then you can hook them up to one of the IOs on the board20:29
tinyfpgadaveshah: I’m using all the IOs I can get out and I suspect most people will not bother with the CC pins due to their complexity20:30
daveshahmakes sense20:30
daveshahMight as well do SBU if you have room20:30
daveshahSmall pads are fine20:30
tinyfpgadaveshah: yeah, I would route them all out20:31
tinyfpgadaveshah: I’ll be putting one or two resistors there as well20:31
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cr1901_modernfelix_: Not yet... all I can say for now :P21:49
cr1901_modernIt'll be easier soon21:50
CarlFKfelix_: are you my LCA roommate felix?21:50
felix_CarlFK: yep22:02
felix_cr1901_modern: sounds promising22:02
CarlFKfelix_: hi!22:08

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