Wednesday, 2018-07-04

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xfxfmithro: when did you want to start talking about the next LCA hackfest?  i need to put costs/a proposal together...06:37
xfxf(assuming you are coming to LCA and want to do the hackfest, of course)06:37
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thaytanxfxf, I'm coming!12:02
xfxfthaytan: to the hackfest?  i'm assuming it's running - hence poking mithro :)12:35
_florent_xobs: in, can you try to add a reset to the UART:12:37
_florent_self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))12:37
_florent_and then in your top module, connect this reset to your Vexriscv reset?12:38
_florent_self.comb += self.uart.reset.eq(your_cpu_reset)12:38
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_florent_that's a workaround, but if that work, it will help us understand what is going on12:39
xobs_florent_: I'll give that a shot.  I haven't tested it today, and I don't have it in front of me right now, but what I was seeing is that when I read the CSR from the softcore, the last value written came back.  Does that make sense?12:56
xobsSo if, for example, the CSR was at address 0xe0000000 (it wasn't), I could write data out the serial port by typing set *0xe0000000='a' in GDB and I'd get an 'a' out the port.12:56
xobsBut then writing 'x 0xe0000000' would return 'a'.12:57
_florent_xobs: that seems strange, if you don't have a loopback somewhere, you should not read back what you write on rxtx register13:02
_florent_xobs: is it the same behaviour before reseting the cpu?13:03
xobs_florent_: It did seem strange to me, too.  But since this is coming from gdb13:03
_florent_xobs: could it be related to the cache?13:03
_florent_xobs: maybe you are reading the cache and not the CSR? which would then make sense13:04
xobsI'll see if I can't patch out the cpu reset from openocd and try it again.13:04
xobsHmm, that's a very very good point.  I should try building the cpu with no cache and see if that changes anything.13:05
xobsThat's probably one of the easier things to do.13:05
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mithroxfxf: It is unlikely that I will have any time to organise the hackfest13:50
CarlFKmithro: I'm up for helping you  organise the hackfest if you think its possible for me to actually help and not just add to your workload13:54
mithroAll my TimVideos stuff is on hold until EOY pretty much13:55
CarlFKany objection to me running a hackfest?  I'll invite you :)13:56
CarlFKhmm, I guess new city means we can't use the same hotel/office .... more on this later.13:57
thaytanmithro, that's perfect - the hackfest is next year! :)13:57
CarlFKmithro: ignore this and that ^^^13:57
CarlFKyes, ignore thaytan :p13:58
thaytanam I not on /ignore already?13:58
CarlFKwhy does my client say someone is talking but no one is talking?13:58
xfxfi can probably do most of the organisation - we may already have a venue/accom14:27
xfxfreally just figuring out what it is we want to do, who should come, and costs, so i can put forward a proposal to LCA14:27
xfxfmithro: hope your project is going well btw14:27
xfxfunderstandable if everything else is on hold!14:27
xfxfmithro: you're coming to pycon au in August aren't you?14:30
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cr1901_modern(8:52:39 AM) xobs: But then writing 'x 0xe0000000' would return 'a'.19:48
cr1901_modernIs gdb's "I/O mirror" or whatever mechanism you use to sniff I/O ports in the 0xe0000000-part of the address space?19:48

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