Tuesday, 2018-06-26

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xobsfutarisIRCcloud: That's what I've got going, yes.  GDB over Ethernet.  The Wishbone interface is super janky, and I suspect it's possible to hook it up much better.  Right now I'm manually strobing the VALID line, for example, and writing directly to both the DATA and ADDRESS registers.02:14
xobsI'm guessing the 8-bit limitation comes from wishbonebridge.py:WishboneStreamingBridge which seems to hardcode 8-bit values.  I think I understand the design reasons behind that decision.02:51
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_florent_xobs: we are using 8-bit CSRs since it seems to reduce resources usage on CSR bus, but you can also use 32-bit CSRs06:18
_florent_you just have to set csr_data_width=32 in the SoC06:19
_florent_if you are using the 8-bit CSRs and want atomic writes, you have to use the atomic write parameter on the CSR register06:19
_florent_the wishbone bridge works for 8-bit and 32-bit, so if you find more convenient to work with 32-bit registers you can use that06:21
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xobs_florent_: I see, thank you.  32-bit access might improve performance for VexRisc-V debugging.  I'll have to check.06:31
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xobs_florent_: Would you be amenable to a patch that replaced MMPTR() in csr.h with a readl()/writel()/readb()/writeb() implementation?  That way I can #include "csr.h" in some code running on my PC and call the accessors in csr.h, as long as I provide an EtherBone implementation of those functions.09:36
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_florent_xobs: yes, that's fine. If you do that, you can add a parameter to the get_csr_header function to enable that.12:48
xobsHmm... I set a 32-bit csr width, but pokes into RAM are only updating the bottom 16 bits.  I wonder if Bunnie used 16-bit DDR, and it's not properly splitting the writes.13:10
CarlFKxobs futaris[m]:   HI!  I have a friend in Chicago that wants to try writing the linux driver side of the "Love-Rusty 3000"  ... and I may be able to find someone to do the fpga side of that...   but I am not lost and need directions ... help?13:37
xobsCarlFK: Love-Rusty 3000?13:41
CarlFK Creating a peripheral providing the Love-Rusty 3000 feature set and adding to your SoC.   https://linux.conf.au/programme/miniconfs/fpga/13:41
tpbTitle: linux.conf.au 2018 - Sydney 22-26 January 2018 (at linux.conf.au)13:41
tpbTitle: Love Rusty 3000 - Techsheet (at docs.google.com)13:41
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xobsHuh.  I don't remember the Love-Rusty bit from the workshop.  Strange.  What do you need direction towards?13:47
CarlFKit was planned to be in the workshop, but got pulled due to non existence  ;)13:48
CarlFKI'm trying to play manager and get people to do the work to make it exist13:49
CarlFKI have a people that wants to work, not I need to give her something to work on13:50
CarlFKI think the goal is for the workshop to include: user space C code -> linux driver C code -> fpga defined hardware  (something outside the linux/soft cpu ... space?)13:53
xobsWell, the general order of operations seems to be Hardware -> Software, so getting the FPGA stuff done first, then poke bits from userspace.14:50
CarlFKsure - but at some point there should be some sort of spec - if that exists the linux driver side can be done now and fixed later if the spec changes15:32
CarlFKgiven I have someone that wants to write the driver right now15:33
CarlFKand if I had said spec, I might be able to get someone to do the hardware side right now too15:33
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TheAssassinmithro: re. scaler thingy: couldnt the netv 2 be suitable for this purpose?23:43
TheAssassin(topic's coming from #voc-lounge)23:44
mithroTheAssassin: If you want 1080p60 as your highest resolution - yes23:44
TheAssassinI assume that's good enough :)23:44
TheAssassinI need to sell this atlys device soon23:44
mithroTheAssassin: Having an Atlys will let you debug if the issue is with the NeTV2 or with the code...23:47
TheAssassinsure... but I guess I'll be more of a consumer of your stuff than being able to contribute23:48
TheAssassinI'm an open source dev23:48
TheAssassinI don't have those 8 hour days where you come home and know "now I have a few hours for other stuff" :)23:48
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TheAssassinmithro: if one of your GSoC in Europe should need an atlys, though, they may contact me23:51
TheAssassinGSoC students*23:51
futarisIRCcloudCarlFK: doing software/firmware/drivers first is doable.  But generally hardware is done first, because it gets "fixed" in a IC first. top down vs bottom up.23:52
futarisIRCcloudCarlFK: For a soft version, write a user-space app, then convert it to a kernel driver. Get someone to write the Verilog / hardware, and replace the soft call in the driver to use the hardware offload.23:53
CarlFKfutarisIRCcloud: to get someone to write anything I need description of what this stuff will do23:56

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