Tuesday, 2018-06-05

*** tpb has joined #timvideos00:00
*** swalladge_ has joined #timvideos00:06
*** swalladge has quit IRC00:07
*** hyadez has quit IRC00:28
*** sb0 has joined #timvideos02:06
*** cr1901_modern1 has joined #timvideos02:08
*** cr1901_modern has quit IRC02:11
*** tumbleweed has quit IRC02:12
*** tumbleweed has joined #timvideos02:14
*** tumbleweed has quit IRC02:14
*** tumbleweed has joined #timvideos02:14
*** hyadez has joined #timvideos02:48
*** DocJosh_ is now known as DrJosh03:11
*** DrJosh is now known as DocJosh03:11
*** rohitksingh_work has joined #timvideos03:44
*** rohitksingh_work has quit IRC04:23
*** rohitksingh_work has joined #timvideos04:25
*** rohitksingh has joined #timvideos05:28
*** rohitksingh has quit IRC05:37
*** cr1901_modern1 has quit IRC05:49
*** cr1901_modern has joined #timvideos05:49
xobsOkay, getting started now on the actual HDL stuff.  I need timing that's faster than 83ns, so I think I'll need to use a PLL.  Is there documentation on how to do that?  I see a Reddit post with some Verilog code from two years ago.06:56
daveshahxobs: have a look at the icepll tool included with icestorm07:00
daveshahThat will create a Verilog module for you07:00
daveshahJust give it input and output frequency07:00
xobsdaveshah: Oh neat.  That looks like exactly what I want.  How to I link to external verilog modules in migen?07:10
daveshahxobs: afraid I don't use migen much, so not sure07:11
*** CarlFK has joined #timvideos07:47
*** ChanServ sets mode: +v CarlFK07:47
*** rohitksingh has joined #timvideos08:22
*** CarlFK has quit IRC08:30
*** rohitksingh has quit IRC08:30
*** Elwell_ is now known as Elwell08:36
*** nancy has joined #timvideos08:44
*** nancy has quit IRC08:56
*** rohitksingh has joined #timvideos09:23
*** rohitksingh has quit IRC09:33
cr1901_modernxobs: Still awake?10:53
cr1901_modernxobs: Here's an example of how to use the PLL: https://gitlab.com/cr1901/fpga765/blob/master/fpga765/platform.py#L49-6510:55
tpbTitle: fpga765/platform.py · master · William D. Jones / fpga765 · GitLab (at gitlab.com)10:55
cr1901_modernYou also need this line: https://gitlab.com/cr1901/fpga765/blob/master/fpga765/platform.py#L9410:55
tpbTitle: fpga765/platform.py · master · William D. Jones / fpga765 · GitLab (at gitlab.com)10:55
daveshahcr1901_modern: I don't think you need the SB_GB if you use PLLOUTGLOBAL, unless you're working around some kind of bug (don't know of any though)10:56
cr1901_modernI don't remember the rules, tbh. And I wrote this code over a year ago10:58
*** rohitksingh_wor1 has joined #timvideos11:02
*** rohitksingh_work has quit IRC11:05
*** f15h has joined #timvideos11:07
xobscr1901_modern: That's about what I got after talking with bunnie, but without the GBUF.  I haven't synthesized it yet, however.11:11
cr1901_modernI don't remember why I put the GBUF there, I prob read it as part of the PLL user guide.11:16
cr1901_modernBut it may very well not be required. I don't actually understand the icestorm docs- they are quite terse.11:17
*** CarlFK has joined #timvideos11:17
*** ChanServ sets mode: +v CarlFK11:17
*** f15h has quit IRC11:50
*** CarlFK has quit IRC12:13
*** CarlFK has joined #timvideos12:19
*** ChanServ sets mode: +v CarlFK12:19
*** rohitksingh_wor1 has quit IRC12:45
cr1901_modern_florent_: When you get the chance, could you upload your repo of your known-to-work lm32-on-tinyfpga?13:02
cr1901_modernI'd like to compare it to mine; last I checked, there was _definitely_ a synthesis mismatch in my repo13:03
*** rohitksingh has joined #timvideos13:03
daveshahyeah, I'd quite like to see that too13:04
_florent_cr1901_modern: i think i just commented these lines:13:04
tpbTitle: litex/lm32_config.v at master · enjoy-digital/litex · GitHub (at github.com)13:04
tpbTitle: litex/lm32_config.v at master · enjoy-digital/litex · GitHub (at github.com)13:04
cr1901_modern_florent_: Yes, but I thought you had a minimum example. I'll go ahead and try your config though13:04
_florent_cr1901_modern: yes this one: https://github.com/enjoy-digital/tinyfpga-soc/blob/master/tinyfpga.py  + the comments on lm32_config.v should work13:06
tpbTitle: tinyfpga-soc/tinyfpga.py at master · enjoy-digital/tinyfpga-soc · GitHub (at github.com)13:06
cr1901_modern_florent_: tyvm13:06
_florent_cr1901_modern: i think i was not running the standard bios but just custom firmware13:08
cr1901_modernThat's perfectly fine right now13:08
_florent_cr1901_modern: because bios was using too much memory13:08
cr1901_modernRight; the next thing I want to do is put your firmware onto flash and see what happens13:09
cr1901_modernBut first I want to confirm things work on my end of course :)13:09
*** rohitksingh has quit IRC13:15
cr1901_modern_florent_: Did you have to do anything special to make your SoC skip building the bios?13:23
cr1901_modernb/c it tries to build the bios anyway when I do "python3 tinyfpga.py", which naturally fails b/c no room13:23
*** rohitksingh has joined #timvideos13:25
cr1901_modernOkay this is weird... the repo falls back to building the bios if firmware.bin can't be found13:25
_florent_cr1901_modern: ah yes, possible13:26
*** rohitksingh has quit IRC13:26
cr1901_modernMust be a litex-ism. I'll check in a bit but my guess is that if integrated_rom_init is empty list, litex tries building the bios13:26
*** rohitksingh has joined #timvideos13:27
cr1901_modernfatal error: failed to place: placed 32 RAMs of 51 / 3213:28
cr1901_modern_florent_:  ^^ Can you check to see if you get this?13:31
*** rohitksingh has quit IRC13:31
cr1901_modernYea I definitely don't see how this firmware fits...13:40
cr1901_modernoh right, forgot to disable cache13:42
_florent_cr1901_modern: ok i look at that13:42
cr1901_modern_florent_: I think I found the issue... I forgot to change lm32_config.v13:43
_florent_cr1901_modern: yes, with that it's fine here13:50
cr1901_modernI'm _really_ surprised the design fits w/ a pipelined multiplier and barrel shifter13:52
cr1901_modernI deliberately disabled those, but I suspect that might be the source of my issues13:52
*** Kripton has quit IRC14:01
cr1901_modern_florent_: I've attached your design + tinyfpga B to a logic analyzer. The LEDs work, but I've got nothing on the UART14:03
cr1901_modernDoes this match behavior you've seen before?14:04
*** Kripton has joined #timvideos14:04
_florent_are you using the right pins for the uart?14:06
_florent_also, have you compiled the firmware?14:07
cr1901_modernas far as I can tell, and firmware is compiled14:07
cr1901_modernCan't be rst signal b/c leds wouldn't be toggling if it was14:13
cr1901_modern_florent_: Could you please test on your end and see if the UART works when you get the chance?14:14
cr1901_modernand if it does, send me the build directory14:14
cr1901_modernI must be configuring something wrong14:14
_florent_cr1901_modern: i'm not able to test now, maybe tomorrow14:16
*** rohitksingh has joined #timvideos14:40
*** rohitksingh has quit IRC15:05
*** fischerm has joined #timvideos15:50
*** Elwell has quit IRC16:02
*** vys_ has quit IRC18:31
*** vys has joined #timvideos18:31
*** Elwell has joined #timvideos21:16
*** Elwell has quit IRC21:22
*** Elwell_ has joined #timvideos21:22
*** tinyfpga has quit IRC21:24
*** tinyfpga has joined #timvideos21:25
*** CarlFK has quit IRC22:05
*** TheAssassin has quit IRC22:08
*** TheAssassin has joined #timvideos22:13
*** swalladge_ has quit IRC22:44

Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!