Wednesday, 2018-05-23

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cr1901_modernmithro, daveshah: Well, this is about as bad of a bug as it gets; simulation says that lm32 on tinyfpga shouldn't be crashing.01:44
cr1901_modernor icebreaker*01:44
cr1901_modernbut of course in reality, it does crash01:44
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mithrocr1901_modern: :-(01:47
mithrocr1901_modern: Timing bug?01:47
cr1901_modernmithro: It's possible, but I have plenty of timing margin. It crashes on the first jump. I guess my next step is to wrap litescope around the design01:50
cr1901_modernThe only "good" thing about this is that the crash is deterministic01:51
cr1901_modern(Or alternatively, I could create a single stepper circuit)01:56
mithrocr1901_modern: Will be interesting to find out why it is failing...02:12
mithrocr1901_modern: You might have seen that I'm trying to get icestorm and arachne-pnr into conda02:17
cr1901_modernThat should be a relatively well-behaved package02:18
mithrocr1901_modern: I want it for the symbiflow-arch-defs02:24
mithrocr1901_modern: For now I had to disable iceprog as it needs libusb and libftdi and I didn't want to put them in a deps at the moment02:24
cr1901_modernWell I think iceprog only works w/ relatively few boards anyway?02:38
mithrocr1901_modern: Dunno...02:51
* cr1901_modern is breaking out part of lm32's addr bus and hoping timing passes02:52
cr1901_modernmithro: Well, I found _something_ that's definitely a simulation/synthesis mismatch03:55
tpbTitle: TinyFPGA LM32 Waveforms - Album on Imgur (at
mithrocr1901_modern: You can make litescope output sigrok traces IIRC....04:03
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daveshahcr1901_modern: this really is weird06:37
daveshahBecause is was crashing in Icecube2 also, so not an icestorm issue06:37
_florent_cr1901_modern:  lm32 was working some months ago on the tinyfpga using icestorm, are you doing something different than what what we where doing some months ago?07:44
_florent_cr1901_modern: if you want i can check if it's still working07:44
cr1901_modern_florent_: If you can create a minimal example that works, please do08:13
cr1901_modernBut right now I don't have the bandwidth to check myself08:14
cr1901_modernFor all I know, we stumbled upon an edge case in the Verilog spec that Xilinx/iverilog can handle, but yosys/icecube can't08:15
cr1901_modern(although IIRC icecube uses synopsys, which I think Xilinx might use?)08:15
daveshahanyway LM32 is made by *Lattice*08:24
daveshahit should work on their own tools08:24
daveshahbut maybe it's actually a Migen/LiteX issue08:24
cr1901_moderndaveshah: Tbf, ice40 was an acquisition from SiliconBlue08:37
daveshahyeah, but the synthesis options are now the same - Synplify or LSE - as Diamond/proper Lattice08:37
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