Thursday, 2018-05-17

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cr1901_modernmithro: Do you still have that litex/migen comparison script?02:18
mithrocr1901_modern: Same place as last time02:33
mithrocr1901_modern: Check my gists -
tpbTitle: mithro’s gists · GitHub (at
mithrohrm apparently it wasn't on my gists...02:35
cr1901_modernYea, just got to the end02:36
mithrocr1901_modern: Hrm... I can't find it :-P02:36
cr1901_modernMy todo list for Migen is filled w/ a bunch of "get Litex and Migen up to feature parity w/ each other" T_T *whines*02:37
cr1901_modernI don't have time to do this, but at least if I had a script, I could see specifically what the differences are02:37
mithrocr1901_modern: Seems to be
tpbTitle: Prepare an upstream migen/misoc for merging into litex · GitHub (at
mithrocr1901_modern: Seems the .gitignore was making it hard to fine02:40
cr1901_modernmithro: Tyvm. This'll put me at ease.02:42
mithrocr1901_modern: I haven't run it recently02:43
mithrocr1901_modern: Feel free to help figure out what still is different02:43
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cr1901_modernmithro: Will do02:43
mithrocr1901_modern: Running home now02:43
cr1901_modernmithro: Leaving a privmsg for later02:43
mithrohey tinyfpga, cr1901_modern is working on tinyfpga_b2 support stuff in litex / misoc02:43
cr1901_modernit's a good FPGA (tm)02:44
tinyfpgaBe back to chat later, my daughter wants to make some chibitronics project :)02:45
cr1901_modernhave fun02:45
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cr1901_modernmithro: Made some changes. Definitely a lot of stuff to do (simulation in particular means litex/migen/misoc will diverge for a while longer)04:15
tpbTitle: Revisions · Prepare an upstream migen/misoc for merging into litex · GitHub (at
cr1901_modernplatforms and _most_ of the backend logic (minus _florent_'s additions to generic_platform such as "Pins() without a constraint string") can prob easily be merged back04:16
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mithrocr1901_modern: I merged the changes?04:30
cr1901_modernmithro: That was the intent :)04:30
cr1901_modernit's not like forking gists is anywhere near as pleasant as repos04:31
cr1901_moderntinyfpga: Btw, tinyfpga_a should follow on migen/litex soon enough. I may need your help tho to test diamond on Linux (assuming you use it).04:32
cr1901_modern(Migen doesn't support diamond on linux at present, but litex does. I want to add this functionality for feature parity, but it may go through a few iterations.)04:32
cr1901_modernsoon enough == a month or so04:32
mithrocr1901_modern: Why do you do ?04:33
tpbTitle: Revisions · Prepare an upstream migen/misoc for merging into litex · GitHub (at
cr1901_modernmithro: If you take it out, sed doesn't make any changes. So the git commit fails w/ "working directory clean".04:34
cr1901_modern(Notice I got rid of the s/migen/litex.gen/g sed command)04:35
cr1901_modernSo I just wrote a substitution that forces sed to make a chance04:35
tinyfpgaAwesome, it will be nice to have both boards supported04:37
mithrocr1901_modern: But you could just remove it if it is no longer needed?04:37
cr1901_modernmithro: I could have :). But I wanted to make the least invasive change possible in case you needed it04:39
cr1901_modernfeel free to remove if you don't need it04:39
cr1901_moderntinyfpga: Do you use Diamond on Linux? I'm in no position to test04:39
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shivm28[m]shorne: Thanks for the information. One more doubt: Why is the field description of Debug Reason Register same as that of Debug Stop Register given in or1k debug unit?05:09
shivm28[m]shorne: For breakpoints, can we say that we are writing the register address of the breakpoint location in the OR1K debug unit. When the program counter matches with this register address, a breakpoint hit takes place?05:14
tinyfpgacr1901_modern: I do most development on Windows unfortunately, but I do have a few Linux boxes that I can try it out on05:20
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tpbTitle: Internals Watchpoints - GDB Wiki (at
shornethis is a pretty good summary on watchpoints and supporting in GDB05:49
shorneshivm28[m]: The DSR and DRR are difference.  DSR is to set which exceptions cause the CPU to hand over control to the Debug Unit (i.e. then GDB)05:50
shorneYou set DSR to turn on debugging, i.e. set the bit for l.trap05:51
shorneThe DRR, it what you inspect when the CPU hands over control to the debug unit. You can inspect it to know if it was a l.trap exception etc05:52
shorneprobably you only need to care about l.trap05:52
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shornemy typos are bad, I hope you understand.05:56
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shivm28[m]shorne: Do we have any document which explains the debug unit of or1k (more information than already mentioned in or1k architecture)? Also, how GDB interacts with the different debug registers?06:08
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akhil_singhrohitksingh_work: I am working on IBERT project. So in IBERT we are trying to calculate BER for transmission error in the transceivers. Now, if we are not using the real FPGA. If we are doing only simulations, then we need to model the error of transceivers. How to do that ?06:29
rohitksingh_workakhil_singh: I believe you want to inject errors into the "simulated" transceiver lanes. For that you could pass the output through a verilog module which would model the physical channel. You can flip some random bits based on the BER you want to test for.06:33
shorneshivm28[m]: the best docs are in adv_debug_sys which I think I provided you before06:34
shorneFor GDB, you might want to read the link I just send06:34
shorneAlso, OpenOCD probably has some good docs.06:34
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rohitksingh_workakhil_singh: that said, simulation can only go so far. For these kind of projects, hardware is really preferable.06:35
akhil_singhrohitksingh_work: Is there any specific way to model the physical channel. Any source to read about it ?06:36
rohitksingh_workakhil_singh: now that is a topic which we shouldn't really go into. I would ask what are your motives for trying to simulate the bit errors?06:39
akhil_singhrohitksingh_work: In my project i have to calculate the bit error, and then control bit error using different things like equalisation etc.06:41
rohitksingh_workakhil_singh: do you have prior knowledge on Xilinx Transceivers?06:42
rohitksingh_workor read anything on those lately?06:42
akhil_singhrohitksingh_work: I have read the documentation, but how to model them in verilog. If the fpga is not used then how do we model all of these ( mainly the physical channel) ?06:46
rohitksingh_workakhil_singh: simplest way to start is to generate an IP using 7 Series Transceivers Wizard. Once that is done, you need to modifiy the sources and bring out TXPOLARITY signal to top module. You can simply invert the TXPOLARITY  randomly to generate errors on the receiver side.06:48
rohitksingh_workakhil_singh: also you absolutely need an FPGA board with transceivers for this project.06:49
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akhil_singhrohitksingh: Okay06:51
rohitksingh_workakhil_singh: When you use IP through 7-Series Transceivers Wizard, it will set up a simple simulation model also. You can use that (with the TXPOLARITY modification). But be warned that, simulating the GTP/GTX transceivers is slow and tedious job.06:52
akhil_singhrohitksingh_work: Okay06:53
rohitksingh_workakhil_singh: you need to get access to an FPGA board with multi-gigabit transceivers (either through university or buy one) as soon as possible. otherwise it will be quite difficult for you without that.06:53
rohitksingh_workokay, great06:54
shivm28[m]shorne: Noted. I am going through all the resources and will get back to you soon.06:55
akhil_singhrohitksingh_work: I can arrange spartan 6, will this be fine ?06:57
rohitksingh_workakhil_singh: 7-series is strongly preferred (ISE is very buggy, plus no updates and support for that. Vivado is way better by orders of magnitude). But if you can't get it in worst case, then you can use 6 series FPGA board. Just do make sure that they have MGT transceivers.07:01
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akhil_singhrohitksingh_work: will zedboard be fine. Though it will be difficult to arrange07:16
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rohitksingh_workakhil_singh: no. Zedboard doesn't have any multi-gigabit transceivers. Make sure to check for boards with transceivers.08:11
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nancy98[m]CarlFK ping .09:56
nancy98[m] tpb09:56
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CarlFKnancy98[m]: im around now14:00
nancy98[m]hello :)  having some issues loading gateware and firmware on opsis for testing14:02
tpbTitle: Ubuntu Pastebin (at
CarlFKnancy98[m]: do you have Opsis or Atlys?14:29
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CarlFKnancy98[m]: un/plug in the usb cable, dmesg, paste the last 20 or so lines (everything after "found new device...")14:33
nancy98[m]yup !
tpbTitle: Ubuntu Pastebin (at
CarlFKnancy98[m]: that is not dmesg14:46
tpbTitle: Ubuntu Pastebin (at
paddatrappernancy98[m]: it looks like it is being disconnected. What is the output of lsusb15:23
CarlFKlots is going on here...15:27
CarlFK[18997.944885] cdc_acm 1-1:1.2: ttyACM0: USB ACM device15:27
CarlFK[19013.413130] wlp2s0: authenticate with b8:c1:a2:49:45:3415:27
CarlFK[19459.777562] usb 1-1: USB disconnect, device number 4715:27
nancy98[m]i get the correct output withmake gateware-load
tpbTitle: Ubuntu Pastebin (at
CarlFKnancy98[m]: dmesg shows the Opsis was disconnected 462 seconds (about 7 minutes) after you plugged it in15:36
nancy98[m]hmm , thought it is connected.. the output of lsusb
tpbTitle: Ubuntu Pastebin (at
CarlFKBus 001 Device 051: ID 16c0:06ad Van Ooijen Technische Informatica15:47
CarlFKthat is the board, in one of the modes - it gets different usb-ids depending on what mode it is in15:48
CarlFKthis is where I get confused and I am not sure what is best to do.  so I turn it off and on again and start over :p15:50
nancy98[m]CarlFK: May i know (i m not sure) if there is coreect JTAG connection15:54
CarlFKnancy98[m]: sorry, I don't use that.  or if I do it is abstracted by mode-switch15:59
nancy98[m]so you turn it off and on again and start over is random16:02
CarlFKI'm sure there is an explanation, I don't know what it is.16:05
nancy98[m]The output of make gateware-load is correct ? or the warning of unbind-helper not found, will have to run as root! has to be considered ..16:08
tpbTitle: Ubuntu Pastebin (at
CarlFKnancy98[m]: is this the last line of output? 62 Found 1 boards.16:15
nancy98[m]Found 1 boards.16:16
CarlFKnancy98[m]: there should be more16:19
CarlFKhmm, maybe I get more because I do: "hdmi2usb-mode-switch -v ..."16:23
CarlFKhere is what my output looks like:
tpbTitle: Ubuntu Pastebin (at
nancy98[m] looking at this i see i  might be facing the same issues , but i have installed udev rules16:30
tpbTitle: HDMI2USB-litex-firmware/ at master · timvideos/HDMI2USB-litex-firmware · GitHub (at
CarlFKWARNING:root:unbind-helper not found, will have to run as root!16:33
CarlFKthat is a warning, so it may not need addressing.  which is frustrating not to know.16:34
nancy98[m]CarlFK:  i think there is issue with udev rules16:39
CarlFKnancy98[m]: I have this: /lib/udev/rules.d/60-hdmi2usb-udev.rules16:44
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