Friday, 2018-03-23

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CarlFK[m]mithro: what USB mic were you sent for the podcast interview?01:15
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futarisIRCcloudWatch "HDDG 28: Optics and FPGAs Tim 'mithro' Ansell - Creating FPGA Based Hardware" on YouTube05:00
tpbTitle: A DIY Nine Channel Digital Scope | Hackaday (at
bunnie_general question -- has anyone experienced a problem where the REPL shell on HDMI2USB firmware crashes after some period of time? Specifically, the main loop with the service() functions continue to run (I can watch status messages being emitted overnight) but the first time I hit enter and send a command to the shell the CPU ends up freezing. Looks like somewhere inside the ci_service() loop but can't tell with any more precision yet...05:21
bunnie_It seems to accept commands for a few minutes. but then if I go away for a few minutes and come back to it, the next command freezes the CPU05:21
bunnie_*for the first few minutes after boot05:21
bunnie_just wondering if this is a "known bug" or if it's something I've done.05:22
cr1901_modernI've left it running for days and when I come back the repl is fine05:27
cr1901_modernBut I don't think I've done "status" overnight05:27
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bunnie_cool. and this is running with video connected, right? I'm suspecting the problem might have to do with a cache lockup or IRQ handling problem due to DMA contention07:03
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cr1901_modernbunnie_: No this was _not_ with the video connected. And I didn't think hdmi2usb had DMA?07:49
cr1901_modern(of course, me not knowing that doesn't mean much :P)07:49
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bunnie_the refererence implementation seems to create a set of frame buffers. On vsync it triggers a DMA engine that writes the data into the current frame buffer, and then that pointer gets updated during the vertical retrace. Both inputs write to different frame buffers, and so when the output switches it just needs to update its read pointer to swap screens.09:34
bunnie_There's an ISR that gets triggered every frame and the CPU is supposed to update that pointer. this runs indefinitely with no trouble.09:35
bunnie_the problem seems to come after a while, if I then try to pass a string into the command line module, it hangs, and I can't seem to figure out why.09:35
bunnie_when there's no video connected, the DMA engines stop. so stability with video connected is different from stability without video09:36
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mithromorning everyone13:33
harshgugaleHello @mithro: Good Morning! Can you please have a look at these questions :!topic/timvideos/eH0c-EEYxVw . Your suggestions appreciated.13:40
tpbTitle: Google Groups (at
thaytanhi mithro :)13:40
mithroHey thaytan -- figured out how to get funded to do FPGA video cores for gstreamer yet?13:40
thaytanmithro, not even a little :)13:40
mithrothaytan: I assume you haven't even thought about it :-)13:41
thaytanbut I did read that the AV1 team are planning on releasing some verilog with the finalised spec13:41
thaytanso that's already happening somewhere!13:41
mithrosadly I doubt they are writing verilog code that is optimized for FPGAs13:43
mithromost probably targeting asics13:44
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thaytanmithro, maybe - but that still reduces the work13:46
shivmmithro: I talked to OSD folk and they advised me focus on or1k CPU core for now. Also, since there is no support of run-control debugging in OSD, major part of the project will be integration of GDB into OSD.13:48
shivmmithro: For off-chip communication, he suggested me to use GLIP, the existing FIFO-based off-chip transport used in OSD. One option would be to integrate GLIP into Wishbone.13:50
mithroshivm: I would want to make sure stuff isn't going to be only tied to the or1k arch13:51
mithrobut concentrating on one architecture first seems like a good idea13:51
shivmmithro: Yes, and I am currently following this diagram:
tpbTitle: Unbenannte Zeichnung - Google Drawings (at
mithroshivm: Option 2 seems like it is probably what we would end up wanting13:55
shivmmithro: Philip suggested me to first focus on adding GDB to OSD and then reaching a solution using GLIP. After that, we can work on custom W2Bhost library.13:57
mithroshivm: Possibly a good idea - I don't know much about that side of things14:01
shivmmithro: Philip is also willing to co-mentor the project. So, I think he can help with those things. Though, I will try my best to cover each aspect but the project involves a lot of research, so is it necessary to provide detailed implementation details of each and every block?14:04
shivmmithro: Here's the thread where I discussed the project with Philip:!topic/timvideos/JFjL-H4dR5M14:06
tpbTitle: Google Groups (at
mithroshivm: As much as you can -- obviously things which change the more details you figure out14:06
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shivmshivm: Yes, for sure.14:17
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CindyCicaleseWMFcarlfk: thanks!15:52
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shivm28mithro: The implementation of or1k in the project firmware is same as that of opencores, right? So, we do have access to debugging registers in the or1k module?16:25
shivm28Can someone please direct me to the github folder where or1k resides in this repo:
tpbTitle: GitHub - timvideos/litex-buildenv: An environment for building LiteX based FPGA designs. Makes it easy to get everything you need! (at
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mithroFYI - My talk from last night is here ->
akhil_singhmithro: For IBERT project, is simple web page for GUI fine or some framework is required ?17:36
mithroakhil_singh: A web based GUI doesn't sound like a bad idea17:40
akhil_singhmithro: is a normal html web page plus css for styling fine ?17:40
mithroakhil_singh: well, it would need to be interactive in the sense you change the settings and see the results17:42
akhil_singhmithro: okay.17:43
mithrobut it wouldn't need to be super fancy really17:44
akhil_singhmithro: I also thought about using gtk17:44
shivm28mithro: The implementation of or1k in the project firmware is same as that of opencores, right? So, we do have access to debugging registers in the or1k module?17:45
mithroshivm28: I think they are disabled at the moment - go look in litex17:46
shivm28But the implementation is exactly same as that of openrisc? So, we can enable that.17:47
mithroshivm28: Go and take a look17:47
akhil_singhmithro: Also i looked what protocols might use high speed transceiver. So basically i came to know that every pattern we generate will have a reference clock and encoding depending on protocol we use.17:47
akhil_singhmithro: Am i right ?17:48
mithroakhil_singh: ?17:51
akhil_singhmithro: will have to encode and provide clock to patterns we generate depending on protocol. right ?17:51
shivm28mithro: Yes, it's the same. Thanks.17:52
akhil_singhmithro: Also the patterns we generate will repeat over time. Am i thinking in right direction now ?17:54
akhil_singhlike for ethernet protocol we will generate PRBS-31, give it a reference clock as that for what actual ethernet will use and then we basically encode that(8b/10b or 64b/66b) before transmitting. Is this correct ?18:13
CarlFKshow in the can.  Opsis was fine.  yay version 19x19:42
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tumbleweedCarlFK[m]: going to declare 19x stable?19:43
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CarlFK[m]On way to airport19:57
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