Friday, 2018-01-26

*** tpb has joined #timvideos00:00
thaytanCarlFK, I don't remember what's inside vocto-core well enough00:01
thaytanbut we could dump the pipeline graph and use that as a reference00:01
CarlFKhttps://github.com/CarlFK/voctomix-outcasts/blob/master/tests/mock-stack.sh00:02
tpbTitle: voctomix-outcasts/mock-stack.sh at master · CarlFK/voctomix-outcasts · GitHub (at github.com)00:02
CarlFKthat is one source, one core, one sink00:02
CarlFKexcept I am pretty sure it doesn't work00:03
CarlFKwould like have something like that so I can swap one of the 3 parts out for a real part that doesn't seem to be working00:04
CarlFKcurrently "no working" makes me wonder which of the 3 parts the problem is in00:04
thaytanooh, and throws gst-criticals00:05
CarlFKummm. sounds good00:05
_florent_stefanor: atlys gateware seems to be ready :)00:07
tumbleweedI'll re-start all the things I cancelled, now00:09
_florent_stefanor: sorry this was for tumbleweed00:09
tumbleweedthey're both me00:10
_florent_tumbleweed: maybe you can test before just on the atlys, because if it's not good we'll have to do another test00:10
thaytanCarlFK, this one works for me (with some gst warnings that don't seem to break anything but I'll look at) https://gist.github.com/thaytan/ff9af88c6abecdfc66e10ccc72d4aacd00:20
tpbTitle: gist:ff9af88c6abecdfc66e10ccc72d4aacd · GitHub (at gist.github.com)00:20
thaytanthe only real difference is including matroskamux in the "server" pipeline00:21
thaytanwhich applies timestamps and caps to the buffers it's receiving00:21
tumbleweed_florent_: it works \o/00:23
tumbleweedthanks00:23
_florent_great00:24
mithrohttps://github.com/timvideos/HDMI2USB-mode-switch/blob/master/libusb_eeprom.py00:32
tpbTitle: HDMI2USB-mode-switch/libusb_eeprom.py at master · timvideos/HDMI2USB-mode-switch · GitHub (at github.com)00:32
*** rohitksingh-demo has joined #timvideos00:37
CarlFKthaytan: thank - I figured it was something simple -00:37
cr1901_modern_florent_: If you don't mind, I'd like to add the DDR3 controller b/c it's about time I learned how to do it: https://github.com/enjoy-digital/litex/pull/6300:45
tpbTitle: boards/platforms: Add Arty S7 Board. by cr1901 · Pull Request #63 · enjoy-digital/litex · GitHub (at github.com)00:45
cr1901_modernmithro: Hopefully SD card fixes done by tonight too00:46
_florent_cr1901_modern: thanks for the pull request. No problem, take your time for the ddr3 controller and feel free to ask questions00:46
_florent_cr1901_modern: this script can be useful for you:00:47
cr1901_modernTy, and will do. I'll def have a few LOL00:47
_florent_cr1901_modern: https://github.com/enjoy-digital/arty-soc/blob/master/test/test_sdram.py00:47
tpbTitle: arty-soc/test_sdram.py at master · enjoy-digital/arty-soc · GitHub (at github.com)00:47
_florent_cr1901_modern: also, in case this script does not report valid bitstlip/delays, you can try to adjust the sys4x_dqs phase00:48
mithro_florent_: Can we get that test_sdram.py script merged into the litedram repo?00:48
_florent_mithro: i'm planning to do it yes00:48
mithro_florent_: Awesome!00:49
cr1901_modern_florent_: Q's like, for instance: What is a bitslip in the context of DDR? :P00:49
_florent_cr1901_modern: the controller is working with sys_clk, but the ddr data are 8 time faster, so bitslip allow you to align the datas you get from ddr to the sys_clk00:51
cr1901_modern_florent_: So it's like HDMI, where the clock is 10x faster? Why doesn't HDMI need something similar?00:52
_florent_cr1901_modern: there is: https://github.com/enjoy-digital/litevideo/blob/master/litevideo/input/charsync.py00:54
tpbTitle: litevideo/charsync.py at master · enjoy-digital/litevideo · GitHub (at github.com)00:54
cr1901_modernHuh... I thought it was the PLL's job to ensure that data was aligned to the clock00:55
_florent_cr1901_modern: do you want to merge the s7 board now or wait you get ddr3 support?00:55
cr1901_modern_florent_: Well, the pinouts are correct, might as well merge it00:55
_florent_cr1901_modern: yes, but that's not the same thing00:55
cr1901_modernit's not?00:56
_florent_cr1901_modern: you have to be sure you are sampling your data correctly00:56
_florent_cr1901_modern: and then align this data to your user clock00:57
_florent_cr1901_modern: run the script i was linking with debug=True and you will understand :)00:58
cr1901_modernI don't think I understand. In the case of HDMI, the 10x clock should _already_ be aligned to the data (or rather, 180 degrees out of phase w/ where you should sample the data)00:58
cr1901_modern_florent_: Will do. I'll do that and come back w/ q's00:58
_florent_rohitksingh-demo: do you want to do some hack on netv2 after lunch?01:05
_florent_rohitksingh-demo: i tried to find the xilinx cable this morning but was not able to find it01:05
rohitksingh-demo_florent_: Yeah!01:14
rohitksingh-demo_florent_: we will try to find it out01:14
*** hyadez has joined #timvideos02:29
felix_rohitksingh-demo: https://github.com/peteut/migen-misc03:00
tpbTitle: GitHub - peteut/migen-misc: Some Migen/MiSoC modules (at github.com)03:00
felix_rohitksingh-demo: https://github.com/jordens/redpid/blob/master/gateware/pitaya_ps.py (that can't be used due to the license)03:00
tpbTitle: redpid/pitaya_ps.py at master · jordens/redpid · GitHub (at github.com)03:00
felix_https://github.com/shenki/linux/commit/9e4dd3846226d649a615708791309d17efa4c530 is probably the right driver for the exar chips03:15
tpbTitle: usb-serial: Add vizzini driver for Exar USB 2 serial adapters · shenki/[email protected] · GitHub (at github.com)03:15
felix_mithro: ^03:17
felix_that one?03:17
mithropaddatrapper: I think you have been making commits?03:54
mithrorohitksingh-demo: Looks like your pull request passes -> https://travis-ci.org/timvideos/HDMI2USB-litex-firmware/builds/333546932 \o/04:07
rohitksingh-demomithro: \o/04:25
rohitksingh-demomithro: where are you currently?05:23
paddatrappermithro: reloaded the OS on my laptop and noticed I had stuff on there I hadn't committed yet. I plan on doing work on the FX2 stuff at the video team sprint next week though06:05
mithropaddatrapper: Ahh cool06:09
*** rohitksingh-demo has quit IRC06:39
*** futarisIRCcloud has quit IRC07:16
*** sb0 has quit IRC08:07
*** futarisIRCcloud has joined #timvideos08:45
*** aps has joined #timvideos08:55
*** danielki has joined #timvideos10:42
danielkihi10:43
danielkiI'm having massive trouble getting our opsis board to sync on an hdmi input10:43
danielkiI've now resorted to feeding the board its own test pattern back to itself, with a super short cable, and it still doesn't get a stable sync10:44
danielkiwith the test pattern fed to itself and then routed to a monitor output, the picture is mostly there, but "fizzly"10:45
danielkiI have tried all variations of firmware, power supply, hdmi cable, etc, to no avail10:46
danielkiit is somewhat better at lower resolutions (= lower pixel clocks), but even then not 100% stable10:46
danielkiso my question: is this a known problem? is our opsis board defective?10:47
*** CarlFK has quit IRC10:48
*** danielki1 has joined #timvideos10:51
*** danielki has left #timvideos10:52
*** danielki1 is now known as danielki10:52
*** danielki has quit IRC10:54
*** danielki has joined #timvideos10:55
*** futarisIRCcloud has quit IRC10:55
*** sb0 has joined #timvideos11:06
*** sb0 has quit IRC11:32
*** aps has quit IRC11:46
felix_xfxf: when are you planning to drive to the blue mountains tomorrow? meey at 9:15 at the breakfast room of the hotel? would also good if you could tell rohit when we'll start13:21
xfxffelix_: unfortunately not anymore sorry, car is still full of equipment and still need to pack equipment tomorrow13:27
xfxfI would like to do something in the afternoon but need to spend the morning at UTS13:28
felix_ok13:32
felix_yeah, sleeping a bit longer will probably good... ;)13:32
felix_so we'll go by train there13:33
*** TimGremalm has quit IRC13:50
*** CarlFK has joined #timvideos14:00
*** ChanServ sets mode: +v CarlFK14:00
danielkiupdate re. my opsis hdmi sync problems: I can get a stable image at "mode 0: [email protected]" with a raspi as the source. only mode that worked so far14:05
xfxfdanielki: are you using a redmere/amplified cable? the opsis requires them14:07
danielkiamplified cable?14:07
danielkioh well, I didn't find anything about that in the docs anywhere :)14:08
danielkiI'm using a 0.5m standard cable currently14:08
danielkithe docs mentioned somewhere that output cables need to be short14:09
danielkibtw increasing the output drive of the raspi didn't make any difference14:10
xfxfhttps://www.monoprice.com/product?c_id=102&cp_id=10255&cs_id=1025507&p_id=9169&seq=1&format=214:13
xfxfwe use the above with conferences, they work well.  even longer ones are fine14:14
xfxfi attached a 20 metre hdmi cable with a joiner and a short redmere cable at the end the other day and worked perfectly for the ~20 hours straight i ran it for at 720p5014:14
xfxfnon-amplified HDMI will give you headaches14:14
xfxfyou also probably want to firmware/gateware flash your opsis to a newer build too if you're running the factory firmware/gateware14:15
danielkialready flashed several different versions14:17
danielkirunning 0.0.4-122 now14:18
xfxfah, cool14:18
xfxfget yourself some redmere cables then, you should have much more success14:18
xfxfwe just used the opsis's in 6 rooms at a conference to record about 160 talks so they certainly work well14:18
danielkialright, thank you, I will have them ordered right away14:18
*** TimGremalm has joined #timvideos14:25
xfxfI'll be in at UTS by around 9.45 by the way14:34
*** sb0 has joined #timvideos15:46
*** olasd has quit IRC16:02
*** olasd has joined #timvideos16:03
cr1901_modern_florent_: Tentatively I figured out a solution to my SD card woes.19:38
cr1901_modernYour firmware assumes that READ_MULTIPLE_BLOCK will terminate by itself. On older SD cards, the correct way to terminate a multiple block read is to send STOP_TRANSMISSION19:39
cr1901_modernIs litesdcard is capable of supporting this while a read is in progress?19:39
_florent_cr1901_modern: since you are targeting an old sd card, so are not wanting performance, i would suggest using single write/reads22:17
_florent_cr1901_modern: it's always difficult to support all the features of a specification and we need to choose22:19
_florent_cr1901_modern: here for low performance and good retro compatibility, i suggest using SPI mode of sd card22:19
_florent_cr1901_modern: litesdcard was mainly designed for high speeds and assume we are using new sd cards22:21
_florent_cr1901_modern: i'll add some informations about that in the README22:21
cr1901_modern_florent_: Regardless, there should be something in the firmware BIST as-is that detects SD card features and then uses the correct rd/wr commands22:26
cr1901_modernI think it's relatively safe to assume that a person who picks out any old SD card from their drawer is gonna find out the hard way that the self-test never terminates.22:27
cr1901_modern_florent_: Does the core itself prevent you from sending another command before the current command finishes?22:28
_florent_cr1901_modern: we can probably do that22:32
cr1901_modern_florent_: If you do that, then we could tolerate SD cards that don't support SET_BLOCK_COUNT. They can send STOP_TRANSMISSION after the relevant number of bytes are read/written22:33
_florent_cr1901_modern: i think it's already supported but needs to be checked22:34
cr1901_modern_florent_: In the meantime, I'll write the code to detect whether SET_BLOCK_COUNT is supported22:35
cr1901_modernSince I have the spec open and it's "just" checking a specific register.22:35
_florent_cr1901_modern: feel free to add features to support old sd cards to the core22:36
cr1901_modernWill do. Also this is an incredibly stupid question, but if _not_ using the BIST, how does code write to the source/sink buffers?22:38
cr1901_modernLooks like w/ the BIST, you start the generator, tell the SDcard command to start a write, and then the SD card core will grab from the BIST one word at a time...22:38
cr1901_modern_florent_: Or do you attach the source/sink to an existing memory on the CSR/wishbone bus?22:42
_florent_you have to have a module that generates 512bytes blocks for writes22:44
_florent_and that consume them for reads22:45
cr1901_modernSo potentially FIFO in/out CSRs would work22:54
cr1901_modernOr more likely, 512 byte memory buffers exposed on the wishbone bus.22:56
*** Peetz0r has quit IRC23:07
*** Peetz1r has joined #timvideos23:07
*** rohitksingh-demo has joined #timvideos23:52

Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!