Monday, 2017-12-11

*** tpb has joined #timvideos00:00
*** rohitksingh_work has joined #timvideos03:47
rohitksingh_workmithro: ping03:50
*** rohitksingh_wor1 has joined #timvideos04:26
*** rohitksingh_work has quit IRC04:27
*** FelixVi has quit IRC05:26
mithroshenki: I'm around now06:04
shenkimithro: hello!06:09
shenkimithro: did you see my question from ~18 hours ago?06:10
mithroshenki: Yes, let me finish getting stuff ready for Rohit06:10
mithroshenki: Did you see that Rusty forwarded a bunch of stuff?06:45
mithroshenki: so Rohit should be all sorted now, so if you want help with the irq stuff I have a little time now...06:50
shenkimithro: okay. can you answer the questions from yesterday?06:51
mithroPossibly06:51
mithroSo, firstly each peripheral has their own "event manager"06:52
mithroThe output of the event managers are logically anded together and wired to the irq pin06:55
mithroshenki: the event manager interface is described in LiteX here -> https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/csr_eventmanager.py06:57
tpbTitle: litex/csr_eventmanager.py at master · enjoy-digital/litex · GitHub (at github.com)06:57
mithroshenki: so my first question is what makes you think the irq you got is for the ethernet and not the UART or other peripheral?07:00
shenkiit triggers when i run the ping command07:00
shenkibut not when I type other characters, nor press buttons07:00
shenkiif i don't enable it, it doesn't fire07:01
shenkiand packets don't get sent from the device07:01
mithroAnd which interrupt are you looking at?07:01
shenki307:01
mithrohttps://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/targets/arty/net.py#L3407:03
tpbTitle: HDMI2USB-litex-firmware/net.py at master · timvideos/HDMI2USB-litex-firmware · GitHub (at github.com)07:03
mithrohttps://github.com/enjoy-digital/liteeth/blob/master/liteeth/core/mac/__init__.py07:05
tpbTitle: liteeth/__init__.py at master · enjoy-digital/liteeth · GitHub (at github.com)07:05
mithroWhich seems to go here07:07
mithrohttps://github.com/enjoy-digital/liteeth/blob/master/liteeth/core/mac/wishbone.py07:07
tpbTitle: liteeth/wishbone.py at master · enjoy-digital/liteeth · GitHub (at github.com)07:07
mithroWhich goes to this bit which has the event manager...07:07
mithroshenki: got a link to your code?07:09
mithroshenki: have you looked at this code? https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/firmware/uip/liteethmac-drv.c#L5407:11
tpbTitle: HDMI2USB-litex-firmware/liteethmac-drv.c at master · timvideos/HDMI2USB-litex-firmware · GitHub (at github.com)07:12
shenkiyes07:12
shenkimithro: http://ozlabs.org/~joel/litex_liteeth.c07:12
shenkithe commented out rx code in liteeth_interrupt doesn't work. but if you run that code, it does send ARP requests over the wire07:13
shenkiif you move the #if 0 down to below the two ioread8's, you will get lots of 0's07:14
shenkiie, the WRITER_EV_STATUS and READER_EV_STATUS always show zero07:14
mithroWhere did you get the gateware from?07:15
shenkii'm running the litex-linux branch07:15
mithroYou built it yourself?07:15
shenki41ddae5085beb36602be41500f0f314affe499eb with the LEDs reenabled07:15
shenkiyes07:15
mithroYou built it yourself?07:16
mithroopps07:16
mithroYou sure you are reading the right memory location?07:16
shenkiYes07:16
mithroCan you add an ioread+print of the LITEETH_EV_PENDING registers?07:18
shenkithey show zero also07:18
shenkias do the ev_enable regs07:18
mithroWell the status registers are likely to always read zero07:19
mithroAs they are instantaneous...07:19
shenkiokay07:20
shenkithe pending registers are zero too, but shouldn't they tell me what the event type was?07:20
mithroshenki: Yes, they should I think...07:21
shenkiokay. how do we work out why that is?07:21
mithroshenki: Which makes me think you are reading either from the wrong location or the wrong byte07:21
shenkiokay. i'm reading the length register incorrectly. I now understand the point _florent_ was making about the byte accesses07:23
mithrohttps://github.com/timvideos/HDMI2USB-firmware-prebuilt/blob/master/archive/master/v0.0.3-1077-g6747572/arty/net/or1k/software/include/generated/csr.h07:23
tpbTitle: HDMI2USB-firmware-prebuilt/csr.h at master · timvideos/HDMI2USB-firmware-prebuilt · GitHub (at github.com)07:23
mithroshenki: https://github.com/timvideos/HDMI2USB-firmware-prebuilt/blob/master/archive/master/v0.0.3-1077-g6747572/arty/net/or1k/software/include/generated/csr.h#L54-L6307:23
tpbTitle: HDMI2USB-firmware-prebuilt/csr.h at master · timvideos/HDMI2USB-firmware-prebuilt · GitHub (at github.com)07:23
shenkii can't see how that would accidently touc hthe pending registers07:23
mithroThe csr register read/writes are a bit funky because it's a 8bit wide bus mapped onto a 32bit wide bus07:24
mithroshenki: Are you reading from the wrong end of the 32bit wide (IE big endian verse small endian?)07:24
shenkino07:25
shenkiI'm doing single byte reads07:25
shenkiso that can't be it07:25
mithroshenki: But which byte are you reading?07:26
mithroiowrite8 only reads one byte right?07:26
shenkicorrect07:28
mithroSo priv->base is something like 0xe0008000 ?07:28
shenkiyes07:28
shenki        mac0: [email protected] {07:29
shenki                compatible = "litex,liteeth";07:29
shenki                reg = <0xe0008000 0x4407:29
shenki                       0xe0007800 0x0a07:29
shenki                       0xb0000000 0x2000>;07:29
shenki                interrupts = <3>;07:29
shenki                tx-fifo-depth = <2>;07:29
shenki                rx-fifo-depth = <2>;07:29
shenki        };07:29
mithroshenki: Notice how each CSR value which is 1 byte wide actually goes up by 4?07:30
mithroshenki: Can you try reading all those 4 bytes?07:33
shenkiwhich four bytes?07:34
mithroshenki: 0x38, 0x39, 0x3a 0x3b07:35
mithroand07:35
mithroshenki: 0x18, 0x19, 0x1a, 0x1b07:36
mithro(First one being LITEETH_READER_EV_PENDING and the second one being LITEETH_WRITER_EV_PENDING)07:36
mithroAlso what are you writing to LITEETH_WRITER_EV_ENABLE ?07:37
_florent_shenki: if you receive the interrupts, that's really strange you don't see anything in pending07:52
_florent_shenki: like mithro, i really think you have to double check you are reading the registers correctly07:53
_florent_shenki: if you are receiving the irq, enable should be set correctly08:01
_florent_shenki: this driver uses pending register for the writer: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/software/libuip/liteethmac-drv.c08:02
tpbTitle: liteeth/liteethmac-drv.c at master · enjoy-digital/liteeth · GitHub (at github.com)08:02
mithroshenki: I'm thinking of heading home / to bed soon08:09
_florent_shenki: in your code, don't use LITEETH_READER_EV_STATUS/LITEETH_WRITER_EV_STATUS08:12
_florent_shenki: but only the EV_PENDING08:12
_florent_shenki: now first thing to fix: if you write 1 to LITEETH_WRITER_EV_ENABLE and don't read 1 from it, there is clearly an issue with your csr access function, no need to go further without fixing that.08:14
shenki_florent_: thanks for the tips. I'll take a close look at it now10:10
*** rohitksingh_wor1 has quit IRC12:35
shenkihrm. can't work out what's going on12:41
shenki[  723.770000] liteeth e0008000.mac eth0: writer bc008018 0012:41
shenki[  725.760000] liteeth e0008000.mac eth0: reader bc008038 0012:41
shenkiI pushed the tree to litex/liteeth-wip at https://github.com/shenki/linux if anyone else wants to try12:41
tpbTitle: GitHub - shenki/linux: Linux kernel source tree (at github.com)12:41
shenkihttps://github.com/shenki/linux/commits/litex/liteeth-wip12:41
tpbTitle: Commits · shenki/linux · GitHub (at github.com)12:41
*** tsglove has joined #timvideos12:44
*** tsglove has quit IRC13:04
*** tsglove has joined #timvideos13:08
shenkiah. MMPTR does a four byte read (it casts the pointer to an int), and the csr.h implicitly casts to a u8, discarding the top three bytes13:09
shenkiso if i change all of my ioread8's to ioread32be, the code Just Works13:09
shenki🔥13:10
*** olasd has quit IRC14:38
*** olasd has joined #timvideos14:39
*** samsagaz has quit IRC15:46
*** samsagaz has joined #timvideos15:46
*** FelixVi has joined #timvideos17:49
mithroshenki: \o/18:00
*** CarlFK has quit IRC18:36
*** CarlFK has joined #timvideos18:37
*** ChanServ sets mode: +v CarlFK18:37
CarlFK[m]mithro: What all was I spozed to do for you when I had time?18:39
mithroCarlFK[m]: test the latest builds and figure out what is going on18:39
CarlFK[m]also poke you about visa paperwork or something like that18:41
CarlFK[m]which reminds me - I think I need to do something for me along those lines18:41
mithroCarlFK[m]: visa paperwork is all done last night18:41
CarlFK[m]yay!  whatever it was :p18:42
mithroTrying to get Rohit into Australia18:42
*** CarlFK has quit IRC18:42
*** CarlFK has joined #timvideos18:42
*** ChanServ sets mode: +v CarlFK18:42
CarlFK[m]that's right18:51
mithroLCA FPGA Miniconf sign up is now open - get in before we start advertising it!20:00
*** bunnie_ has joined #timvideos21:53
*** Joelw_ has joined #timvideos21:53
*** Kamilion|ZNC has joined #timvideos21:55
*** Kripton has quit IRC21:58
*** bunnie has quit IRC21:58
*** Joelw has quit IRC21:58
*** paddatrapper has quit IRC21:58
*** Kamilion has quit IRC21:58
*** Kamilion|ZNC is now known as Kamilion21:58
*** Kripton has joined #timvideos21:59
*** paddatrapper has joined #timvideos22:01
*** tpb has joined #timvideos23:58
*** mithro has quit IRC23:58
*** Signotheque has quit IRC23:59
*** tumbleweed has quit IRC23:59
*** ivodd has quit IRC23:59

Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!