Monday, 2016-12-26

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paddatrappermithro: I've had no Internet for about the past week, but hope to get somewhere by the end of the week03:42
paddatrapperCarlFK: they are called system facts. A full list is here:
tpbTitle: Variables Ansible Documentation (at
CarlFKpaddatrapper: thanks - knowing the right terms helps04:43
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mithrotumbleweed: Ping me when you are in Hamburg :-)11:15
tumbleweedmithro: ack. I land at 311:18
mithrotumbleweed: Where are you staying?11:45
tumbleweedmithro: an airbnb, fairly near by11:59
mithroI'm at the Marriott12:01
tumbleweedok, I think that's in the opposite direction, but still pretty close12:04
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mithrocr1901_modern: ping?15:27
cr1901_modernmithro: pong15:28
mithrocr1901_modern: How's things going?15:28
cr1901_modernmithro: I'm kinda stuck. I'm reflashing the scope firmware and I'll play with an IPython notebook.15:29
mithroI've been thinking about if having gdb support would help15:30
cr1901_modernmithro: It may very well help, but something else is bothering me15:31
cr1901_modernmithro: LM32 has a cache. It should be caching everything read from flash15:35
cr1901_modernWhy would a value read from cache be different when its read a second time?15:35
mithrocr1901_modern: no idea15:35
cr1901_modernmithro: Is the ROM section uncached?15:36
mithrocr1901_modern: NFI....15:36
cr1901_modernI may need to simulate parts of the CPU in iverilog.15:38
tpbTitle: spi_flash: fix bitbang with spi_width=1 by mithro · Pull Request #14 · enjoy-digital/litex · GitHub (at
mithrocr1901_modern: There is a "sim" target which uses verilator15:47
cr1901_modernmithro: Re: that pull request... I'm not sure it works. For 1-bit width, I think the MiSoC fix doesn't send the data down miso15:49
mithrocr1901_modern: Can you put a comment on it15:49
cr1901_modernmithro: Done. (Albiet poorly formatted)15:58
ysionneaucr1901_modern: what's your problem with lm32 exactly ?18:47
mithro[mithro/HDMI2USB-litex-firmware/nextgen#60] (d801073): The build passed. (
mithroysionneau: He is trying to get the bios to boot from spi flash directly19:29
mithro_florent_: ping?19:56
mithro_florent_: Currently got access to a NeTV2 board and trying to get the BaseSoC to boot19:56
ysionneaumithro: is he sure that what he reads from flash is correct first?20:22
ysionneauhe can try booting a small BIOS from blockram and then do mr to read the flash from the bios cmd line20:22
mithroysionneau: We just use the wishbone uart bridge to read the spi flash20:27
mithroysionneau: That was returning the contents expected20:27
ysionneauhmmm ok, weird20:29
ysionneauis the code on some github branch?20:30
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mithroysionneau: I can forward what I sent cr190120:47
ysionneaumithro: yep I can have a look :)20:47
mithroysionneau: email sent20:49
ysionneaugot it thx !20:50
mithroysionneau: Oh and
tpbTitle: spi_flash: fix bitbang with spi_width=1 by mithro · Pull Request #14 · enjoy-digital/litex · GitHub (at
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CarlFKWhy would a value read from cache be different ....  Can the cache be disabled to see if that fixes things? (hoping this is easy to try and easy to see results)22:22
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