Sunday, 2016-10-23

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mithro_florent_: ping?08:46
_florent_mithro: hi08:52
mithroshenki: is currently trying to get the opsis-soc stuff working on the minispartan6 because he is too lazy to carry around an opsis08:52
cr1901_modernDoes shenki need help?08:55
_florent_mithro: ok, I'll work next week on the project, I can also try to get that working08:57
mithro_florent_: Well, I'd like to concentrate on the opsis stuff - did you see the meeting invite for Thursday - is that something you could make?08:58
_florent_mithro: yes that's fine08:58
mithro_florent_: My weeknights get busy pretty quickly, so wanted to block that off so we actually get around to doing it08:58
mithro_florent_: The weirdness around CSR registers and status output things is probably the next thing I would look at tackling08:59
mithro and
tpbTitle: DDR status output is bogus · Issue #22 · enjoy-digital/opsis-soc · GitHub (at
_florent_mithro: ok, I'll work on that (probably tomorrow)09:01
mithro_florent_: Okay - I haven't looked into it very much09:07
shenkiBIOS> memtest10:29
shenkiMemtest bus failed: 128/256 errors10:29
shenkiMemtest data failed: 392998/524288 errors10:29
shenkiMemtest addr failed: 4096/8192 errors10:29
shenkiwhat does that look like?10:29
shenkiaside from about half errors10:30
mithroshenki: Maybe go and look at what the bios code does?10:31
shenki        for(i=0;i<MEMTEST_BUS_SIZE/4;i++) {10:31
shenki                array[i] = ONEZERO;10:31
shenki        }10:31
shenki        volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;10:32
shenkiit writes a word of 0xAAAAAAAA to each address starting at MAIN_RAM_BASE and going to MEMTEST_BUS_SIZE (aka 512)10:33
mithroBe back in a bit, have to go find dinner and head home10:36
mithroshenki: I wonder if it is something like the sdram is only being 16bits wide or something?10:36
mithro_florent_ and cr1901_modern might know more10:37
mithrocr1901_modern: Have you tried litedram with the minispartan6+ at all?10:37
mithroshenki: might want to compare to10:42
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at
mithroBut I can see anything majorily different10:43
mithroshenki: this is what the sim target does..
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at
shenkii edited the memtest to print more info, and rebuilt10:45
shenkibut the changes aren't appearing on the hardware10:45
shenkii saw it rebuild the source10:45
mithroDid you reload it with openocd?10:47
mithroThe bios is embedded in the gateware10:48
shenkiyeah, i reloaded10:48
shenkipower cycled too10:48
shenkiok, make clean worked10:50
shenkimithro: the test has errors in it's calculation10:51
shenkiit is all fine if you have zero failures10:52
shenkibut the number of memory locations is incorrect10:52
mithroDoesn't the make file rm -rf the whole build directory currently?10:52
mithroYou remove that?10:53
shenkii did that10:53
shenkiand when i rebuilt the firmware was rebuilt properly10:54
mithroSo where are the errors occurring?10:56
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shenkihrmm, it's working now11:13
shenkiverrrry strange11:13
shenkiwhen it was failing, it was only a byte here and there in every word11:14
shenki[FLTERM] Done.11:14
shenkiExecuting booted program.11:14
shenkiOpsis CPU testing software built Oct 23 2016 21:33:0311:14
shenkican't type any input11:14
mithroshenki: hrm11:20
mithroshenki: I wonder if there is some type of marginal timing issue with the sdram?11:21
mithroThe firmware is executing in a loop, so it's more likely to error out11:22
mithroWe really need a "ram hammer" type tests11:27
shenkiyeah, when i regenerated it's broken11:27
shenkiso we aren't tight enough with some of our timing11:28
mithro>>> bin(0x8e2d7602)11:28
mithro>>> bin(0x8ead7602)11:28
mithroThat is a single bit flip?11:28
shenkisome of them are. some are more than one bit11:31
shenkimost of the time it's in the one byte11:31
mithroshenki: want to port to misoc :-P11:37
tpbTitle: MemTest86 - Offical Site of the x86 Memory Testing Tool (at
mithroActually I wrote a bunch of stuff on that at
tpbTitle: Create memory performance and error testing solution · Issue #153 · timvideos/HDMI2USB-misoc-firmware · GitHub (at
mithroThe does "        self.platform.add_period_constraint(self.crg.cd_sys.clk, 1/clk_freq*1e9)"11:41
mithroshenki: Probably need something like that in too11:43
shenkimithro: ./litex/boards/targets/ doesn't have the base50 clock that our board has11:50
mithroI don't think base50 clock is used at all in
shenkinup. i removed it11:54
mithroshenki: something like
tpbTitle: Adding period constraints. · mithro/[email protected] · GitHub (at
shenkiit managed to build a working bitstream again. still not accepting input11:56
shenkican we blink a led in the mainloop or something?11:59
mithroshenki: That is on the todo list :-P12:00
mithroshenki: it should be pretty quick to edit the firmware and reload it12:00
mithroshenki: Just hit the reset button rather then power cycling and flterm to load the new code12:00
shenkiwe need to write a watchdog :)12:03
mithroshenki: and
tpbTitle: Make the ATX case panel LEDs/switch work on the Opsis by mithro · Pull Request #277 · timvideos/HDMI2USB-misoc-firmware · GitHub (at
mithroanyway, bed time for me12:21
shenkimithro: night! thanks for your help12:31
shenkicrashing just after starting the firmware again13:20
shenkiif i revert the top commit, it goes ok13:20
tpbTitle: Commits · shenki/opsis-soc · GitHub (at
shenki[FLTERM] Upload complete (10.3KB/s).13:21
shenki[FLTERM] Booting the device.13:21
shenki[FLTERM] Done.13:21
shenkiExecuting booted program.13:21
shenkiOpsis CPU testing software built13:21
shenki(hangs there)13:21
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