Tuesday, 2016-08-09

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xfxfmithro: when you're up, can you msg me the IP of my connection?02:12
xfxfwoo dynamic ip's02:12
mithroJust about to get up now02:13
mithroDid you see my note about the fuse?02:13
mithroCarlFK: did you get any where?02:14
CarlFKmithro: just hooked it up, fumbling  to get my tester app going02:15
CarlFKImportError: No module named serial02:15
CarlFKany idea what the python3 name is?02:15
sb0still serial02:18
xfxfmithro: i did, i think the heaters are tripping it.  turned the one off in the office, turn the one off in your room too if it's on02:18
xfxfthat circuit has a 20A fuse on it, i somehow doubt we're pulling more than that02:19
xfxfCarlFK: iirc that's not std library - pip3 install pyserial ?02:20
CarlFKSuccessfully installed pyserial-3.1.102:22
CarlFKImportError: No module named serial02:22
CarlFKer,  pip3   missed that... maybe02:22
CarlFKRequirement already satisfied (use --upgrade to upgrade): pyserial in ./.virtualenvs/veyepar/lib/python3.5/site-packages02:22
xfxfCarlFK: i just had the same problem on OS X02:27
xfxftry this02:27
xfxfpython3 -m pip install pyserial02:27
xfxfmy pip3 was pointed to a different python installation than my python3 in my path02:27
xfxfabove solves it02:27
xfxfyou probly want to use pyvenv with python3 was well, not virtualenv02:27
xfxfmithro: poke, IP address pls (the box i normally bounce to is off)02:30
CarlFKxfxf:  are you sure it is serial and not pyserial?02:32
xfxfpretty sure yes02:33
xfxflook inside of site-packages if you want to verify, it's just python after all02:33
CarlFKum.. look for what?02:34
xfxfalternatively you probably have a python3-serial package or something if you're on debian/ubuntu and you don't mind installing it globally02:35
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mithroHeyo rohitksingh_work04:30
rohitksingh_workmithro: hi!04:30
mithrocr1901: So, were are we at with your pull request?04:33
cr1901mithro: Still writing the docstrings. Might as well finish that before I go to bed.04:34
cr1901mithro: Provided my energy doesn't give out, let's go ahead and get this merged before I retire for the night04:35
mithrocr1901: That would be awesome04:36
mithroCarlFK: Did you see the frequency counter stuff I linked?04:36
mithroCarlFK: It lets you see the pixel clock frequency even when the the video data is out of range04:36
cr1901Then I need to make a post to EE.StackExchange... yay :/04:37
mithroCarlFK: IE If someone is sending 1080p60 resolution, you can see the pixel clock frequency04:37
CarlFKmithro:  something chanege and confused my tester...04:38
mithroCarlFK: was it the v0.0.2 tag?04:38
CarlFKmithro: don't know.. digging.. here is the log so far:04:39
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)04:39
mithroCarlFK: that looks right?04:40
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mithrorohitksingh_work: Where are we at with the VGA gateware do you think?04:47
rohitksingh_workmithro: there is now merge conflict in atlys_video target i guess04:48
mithroCarlFK: what does "nodir" mean? I assume it means that revision doesn't have a file for the Atlys?04:48
CarlFKmithro: correct04:58
mithroCarlFK: It looks like the "fixed" pull request only just made it to the prebuilt repo05:15
CarlFKmithro: im done for the day.. brain is 1/2 asleep.. can you give me the commands to test to see if it boots?05:18
mithroCarlFK: I'm not sure how you do it, I'm pretty sure you do it differently to how I would...05:24
CarlFKmithro: how would you do it?05:24
mithroCarlFK: "make load-gateware" on a checkout of the HDMI2USB-misoc-firmware repo05:24
CarlFKoh right.. I don't have any of that installed05:25
mithroI think you have been using openocd or modeswitch?05:25
cr1901mithro: Two classes left to document05:25
CarlFKmithro: both.  (which surprises me)05:26
CarlFK    run_cmd(["hdmi2usb-mode-switch", "--mode=jtag"])05:27
CarlFK    run_cmd( ['openocd', '-f', 'board/digilent_atlys.cfg',05:27
CarlFK            '-c', "init; pld load 0 {}; exit".format(fp) ] )05:27
CarlFKah, I get it05:27
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mithroCarlFK: in theory you should just be able to do "hdmi2usb-mode-switch -v --load-gateware {}".format(fp)05:31
CarlFKmithro: what dir/ver should I be using?05:34
CarlFKHDMI2USB-firmware-prebuilt/archive/master/v0.0.2-63-g24c11c0/atlys  no hdmi2usb05:34
CarlFKmithro: why did the counter seem to go from 701 to 16?05:35
mithroCarlFK: what do you mean?05:35
mithroCarlFK: oh, because the number is "number of commits since the tag"05:36
mithroCarlFK: so when v0.0.2 was tagged the number resets05:36
CarlFKmithro: 63 a 3 digit number at 70105:36
CarlFKbash: cd: v0.0.2-63-g24c11c0/atlys/hdmi2usb: No such file or directory05:36
CarlFK no hdmi2usb05:36
tpbTitle: HDMI2USB-firmware-prebuilt/archive/master/v0.0.2-63-g24c11c0/atlys/hdmi2usb at master · timvideos/HDMI2USB-firmware-prebuilt · GitHub (at github.com)05:37
CarlFKmithro: ah, git pull, it is there now05:37
CarlFKmithro: it boots05:40
CarlFK  git describe: v0.0.2-63-g24c11c0-dirty05:40
mithroCarlFK: As I mentioned I wanted you to do a bunch of actual testing on the 3 revisions I listed05:41
CarlFKmithro: that  will have to wait till tomrorow.  I'm having trouble typing05:42
mithroCarlFK: okay05:48
CarlFKabout 1a, Ill be up in 6 hours.05:48
cr1901mithro: Check now05:56
cr1901I'm brushing my teeth while I wait :P05:56
mithrocr1901: Give me a little bit, just in the middle of finishing something06:02
cr1901mithro: How long? I need to be up in 4-5 hours06:05
mithrocr1901: Looks good06:06
mithrocr1901: Just one small change06:06
mithrocr1901: I think some of the modules you have in the module already have existing migen/misoc primitives - but lets not block on that for now06:07
cr1901mithro: They do in the old API. I wrote this to be easy to change when you went to the new API. But since that's prob not gonna happen anymore, you're right.06:08
mithrocr1901: Hrm? We still plan to move towards the new migen/misoc/litex06:08
cr1901mithro: Ahhh, I thought you were now only targeting Litex06:09
cr1901which is "a continuation of the old API", AIUI06:09
mithrowell, litex is suppose to be compatible with migen/misoc?06:09
cr1901The old API06:09
cr1901_florent_: Feel free to disagree with me here :P06:09
mithrolitex has some stuff backported/kept around06:09
cr1901Well, it can prob safely be changed06:10
cr1901mithro: Unfortunately, right now I'm not in a position to test it. My minispartan board isn't here, and this isn't a powerful netbook. I would expect building a bitstream to take upwards of 20 minutes06:10
mithrocr1901: It works last I tested it06:11
mithrocr1901: I can test again shortly06:11
cr1901mithro: Very well, fixing it now06:12
cr1901mithro: Sorry, energy's fading. I can't do it right now :/06:19
mithrocr1901: okay, have a good night06:23
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xfxfthaytan: my usb audio is getting totally out of sync with my v4l video :/  any ideas?09:49
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mithroHey, ssk1328 how is it going? Getting anywhere?12:15
ssk1328mithro: Yeah12:15
ssk1328mithro: Working on the new HDMI_OUT rework12:15
ssk1328mithro: With direct connections in the mixer block12:15
ssk1328mithro: Right now trying to fix a bug12:15
ssk1328mithro: I created a separate branch for this12:16
mithroHow is that going? Anything I can help with?12:16
ssk1328mithro: https://github.com/timvideos/migen/blob/ad57f636eb95c0c0ba539fe9048266120f3f5c54/migen/flow/plumbing.py#L1912:17
tpbTitle: migen/plumbing.py at ad57f636eb95c0c0ba539fe9048266120f3f5c54 · timvideos/migen · GitHub (at github.com)12:17
ssk1328mithro: When trying to use this COmbinator block12:17
ssk1328mithro: WHat format is subrecord supposed to be in12:17
ssk1328mithro: I tried a list of layouts, but that didn't compile12:18
mithroI think it's a list of strings12:18
mithroIt's a list of things that layout_partial arguments actually12:19
ssk1328mithro: list of strings mught make sense12:21
mithroIt's a list of tuples12:22
mithroWhere the tuples are arguments you would give to the layout_partial function12:22
RattusRattusmithro: hay again.  Finished schematic review for TOFE VGA expansion board.  where would you like me to post comments?  I see from earlier that you suggest to CarlFK I should post patches.  Not sure how to do that (yet) but would be happy to do so with help.  Although I suspect reading comments would be a good first step...12:22
tpbTitle: migen/record.py at fa3537d0e0909807c5f5fb3858e175b3a4545acb · m-labs/migen · GitHub (at github.com)12:24
mithroRattusRattus: maybe post it in a Pastebin first, and then create GitHub issues for the major items?12:25
mithroRattusRattus: https://github.com/timvideos/HDMI2USB-TOFE-VGA/issues/new12:26
tpbTitle: Sign in to GitHub · GitHub (at github.com)12:26
RattusRattusmithro: ta!12:27
mithroRattusRattus: you can modify the schematic and send a pull request if you wanted to12:28
RattusRattusmithro: not done this GIT thing before....12:28
mithroSadly, it's not that easy to do merging, so tell me if you are doing that12:29
mithroRattusRattus: have you done svn?12:29
RattusRattusindeed.  well lets start with a paste of comments and take it from there....12:29
RattusRattusone moment12:29
mithroGitHub have a way to access git repository with svn if you would prefer, otherwise I can walk you through the basics12:32
mithroI'm on a train currently12:34
thaytanxfxf, no, that's a case that should definitely work fine12:34
mithroBut will be back in xfxf's place in ~20 minutes12:34
RattusRattushttp://paste.debian.net/787612/  << Comments12:35
tpbTitle: debian Pastezone (at paste.debian.net)12:35
* RattusRattus is happy to do updates, so I guess I'll need a walk through on GIT. Will need to do that from home though (at work right now)12:36
xfxfthaytan: hrm. any ideas? i'm running out of them :/12:37
thaytanxfxf, what's the setup in that case? same? 2 source elements in 1 pipeline sharing a clock? Does the audio source have a slaving method set?12:38
xfxfI'm picking up mithro from train - I'll be home in 15 and will put the pipeline as a simple gst-launch line in a single script12:44
xfxfIt's currently the Python script I pasted earlier, which takes a v4l stream and a alsa or pulse stream and muxes them into the uncompressed format vocto requires12:45
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CarlFKthaytan: this, plus maybe this added to the audio src:  provide-clock=false slave-method=resample12:57
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)12:57
mithroRattusRattus: looking at your comments now13:03
thaytanthose should never drift out of sync, although it could be handy to put audiorate in the audio path as well, to insert or drop audio samples13:03
thaytanwith no queue in place there, you've only got 200ms of buffering inside ALSA before you'll lose samples13:03
thaytanso a subtantial delay in the muxing or transmitting could cause you to miss samples13:04
thaytanI'd add a queue and an audiorate element13:04
xfxf@thaytan: the actual script i'm using is here: https://github.com/xfxf/voctomix-outcasts/blob/master/ingest.py13:05
tpbTitle: voctomix-outcasts/ingest.py at master · xfxf/voctomix-outcasts · GitHub (at github.com)13:05
xfxfwhich is like the one carl pasted but with some additions13:05
xfxfoh nm, he's pasted the actual pipeline it constructs13:05
xfxfso indeed, as above13:05
thaytanso, because both audio and video are timestamped off the same clock, you should not get drift in the resulting mkv file13:06
thaytanbut there might be gaps from missed audio if the network delays anything13:06
xfxfdefinitely getting drift13:06
thaytanso there might be jumps in the timestamps, even though things are in sync13:07
xfxfthis is from the same machine13:07
xfxfnot over network13:07
thaytanif anything then treats that audio stream as continuous, it would drift out13:07
thaytanxfxf, can you record the exact incoming mkv file to disk?13:07
xfxfhmm, https://github.com/xfxf/voctomix-outcasts/blob/master/ingest.py#L24713:07
tpbTitle: voctomix-outcasts/ingest.py at master · xfxf/voctomix-outcasts · GitHub (at github.com)13:07
xfxfwould the set_offset()'s be causing any issues?13:07
xfxfi was using those on my latest test/run13:07
xfxfbecause the audio comes in slightly later than the video, so delayed the video slightly (--video-delay 200 to that script)13:08
xfxfthaytan: re recording exact incoming mkv file, i tried that, but because it's uncompressed video/audio, i run out of disk I/O13:09
xfxfi'm now trying the same thing with a filesink, but with a 'videoconvert' and 'audioconvert' after the raw lines, with mpeg2 encoders13:10
xfxfwhich isn't exactly the same but i think it's the closest i can do13:10
thaytanxfxf, if you delay the video by 200ms, you're really pushing the friendship13:10
thaytansince 200ms is the default buffersize for alsa / pulse sources13:10
thaytanso now that buffer will run seriously close to full all the time, waiting on the muxer to mix things13:11
xfxfright, unfortunately, there is a delay between the video and audio so i needed to do that so i have lipsync13:11
xfxfshould i increase the buffer size?13:11
thaytanagain, add a queue13:11
thaytanbetween alsasrc and the muxer, like in the video chain13:11
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)13:11
xfxfthaytan: like the above, sans the mpeg2 lines?13:12
xfxf(that's what i'm using to try and replicate this issue locally without vocto)13:12
xfxfer, there was a queue there, sorry, i'll re-add it13:12
thaytanthat's not the same as what carl posted13:12
thaytanhis had a queue in the video chain13:13
mithroRattusRattus: What is the best way to respond to these things?13:13
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)13:14
xfxflike that, or stick the queue elsewhere?13:14
RattusRattusmithro: lol.  here?  I did look for a mailing list but that appears to be for software.13:15
RattusRattusbrb - impromptu office  meeting13:17
mithroRattusRattus: so you're one of these people who like small value resistors on their digital IO lines, huh?13:21
ssk1328mithro: HDMIOut rework works, mixer block is connected directly right now13:23
ssk1328mithro: No I will need to add pipeline modules in Mixing block13:23
mithrossk1328: I'm not sure what that means?13:23
ssk1328mithro: So mixer block is a dummy is just connects the first input to output13:24
ssk1328mithro: Now I am adding floatadd modules to mixer block13:24
ssk1328mithro: And other floatmodules13:24
mithrossk1328: Can you push the changes with the dummy mixing block?13:25
ssk1328mithro: In minute13:25
ssk1328mithro: https://github.com/ssk1328/HDMI2USB-misoc-firmware/tree/hdmiout_rework/gateware13:27
tpbTitle: HDMI2USB-misoc-firmware/gateware at hdmiout_rework · ssk1328/HDMI2USB-misoc-firmware · GitHub (at github.com)13:27
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mithroRattusRattus: http://paste.debian.net/787629/13:47
tpbTitle: debian Pastezone (at paste.debian.net)13:47
mithroRattusRattus: the tpd7s019 does look like it might be a good idea13:50
mithrossk1328: what is a "Combinat" ?13:53
ssk1328mithro: I tried making the Combinator work, but that didn't, so using this for now13:54
mithrossk1328: You should give it a proper name :P13:55
xfxfthaytan: https://github.com/xfxf/video-scripts/blob/master/pycon/test-hdmi2usb-capture.sh13:55
tpbTitle: video-scripts/test-hdmi2usb-capture.sh at master · xfxf/video-scripts · GitHub (at github.com)13:55
xfxfeach has a queue now, and i've added 'audiorate'13:55
ssk1328mithro: self.combiner was intuitive enough13:56
xfxfam testing this + simultaneously the same thing within vocto without the last 2 lines on each src (Xconvert, mpeg2 line)13:56
mithrossk1328: You should also just pass in the crossbar and have the PixelGather call "getmaster" n times13:56
xfxfdoes that look OK?13:56
ssk1328mithro: Yeah, i was waiting to add that in for loop13:57
ssk1328mithro: Any good way to get rid of pack_factor dependency on lasmim.dw13:59
ssk1328mithro: Actually I figured out14:01
thaytanxfxf, yes, looks OK to me14:02
xfxfthaytan: cool, ta.  would you advise any of the slave-method's over the other?14:04
xfxfi'm using re-timestamp now, was using resample before, same issue14:05
tpbTitle: voctomix-outcasts/ingest.py at master · xfxf/voctomix-outcasts · GitHub (at github.com)14:05
mithroThat slaves the vocto mix pipeline to the network clock14:05
mithrowhat does     clock.wait_for_sync(Gst.CLOCK_TIME_NONE)  do?14:06
thaytanxfxf, no, as long as it's not "none"14:10
thaytanmithro, waits until the slaved clock has managed to sync to the master14:10
thaytanwith infinite timeout14:10
thaytanso it'll sit forever if the master is firewalled or otherwise unavailable14:11
mithrothaytan: In a pipeline like xfxf's what would happen if the v4l src isn't getting frames at a constant frame rate?14:15
thaytanmithro, the videorate element will drop / repeat frames to make a constant framerate stream14:16
thaytanbut only when a frame actually arrives - there's no timeout mechanism to trigger it if frames are really far apart, for example14:16
thaytanyou handle that case on the server side14:16
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xfxfmithro: should i be trying your latest firmware in master?14:27
mithroxfxf: sure14:28
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* RattusRattus returns14:33
RattusRattusmithro: yes - series termination resistors make a huge differance.  They are especially usefull on high speed signals.  they improve noise immunity and, if coupled with controlled impeadance tracking, reduce emmissions as well14:35
ssk1328mithro: You around for some discussions regarding mixer block?14:36
ssk1328mithro: Apparently having to add mixer block before VTG doesn't make a lot of sense now14:37
ssk1328mithro: Our document for reference https://docs.google.com/document/d/1g1c2IwCVxVzSHWdXbZ746HP-fnM4y1WqFuBZNkLi5mw/edit#heading=h.4gwktoqxm2hh14:37
tpbTitle: Mixer Block Design - Google Docs (at docs.google.com)14:37
mithroRattusRattus: I've seen them cause almost as many problems as they solve14:38
mithrossk1328: sure, why do you say that?14:38
ssk1328mithro: The pipelines modules all run at pixel clock, so need to define all the clocking things here14:40
ssk1328mithro: Plus, before FIFO of Driver, each token is #pack_factor number of pixels14:40
ssk1328mithro: So pixel clock doesn't make sense here14:41
mithrossk1328: Looking at the diagram, the Unpacker is what converts the pack_factor number to individual pixels14:42
mithrossk1328: that is before the VTG14:42
mithrossk1328: The HDMIOut should just take a stream of pixels + the VTG signals14:42
mithroIE HDMIOut == the DAC part of the system14:43
ssk1328mithro: No, see the pixel_layout() in format.py,14:43
ssk1328mithro: I hope the pack_factor value for our DMA is more than one14:44
mithrossk1328: What are you saying no too?14:47
ssk1328Unpackes doesn't convert it into individual pixels14:48
CarlFKthaytan: to help us test the vocto stuff, I am trying to mock out the vocto code with gst-launch commands.. but this doesn't work: https://github.com/CarlFK/voctomix-outcasts/blob/master/tests/mock-stack.sh14:48
tpbTitle: voctomix-outcasts/mock-stack.sh at master · CarlFK/voctomix-outcasts · GitHub (at github.com)14:48
CarlFKmatroska-demux.c(4489): gst_matroska_demux_parse_id (): /GstPipeline:pipeline0/GstMatroskaDemux:demux:  Invalid header14:48
mithrossk1328: what does unpack do then?14:48
ssk1328mithro: Some combinatorial connections, nothing sequential14:49
mithrossk1328: Why does it exist?14:50
ssk1328mithro: I guess cast is the equivalent of unpacker here https://github.com/timvideos/HDMI2USB-misoc-firmware/blob/master/gateware/hdmi_out/__init__.py#L3014:50
tpbTitle: HDMI2USB-misoc-firmware/__init__.py at master · timvideos/HDMI2USB-misoc-firmware · GitHub (at github.com)14:50
ssk1328mithro: It just connects data_width worth of data to our pixel_layout14:51
thaytanCarlFK, you can't set clocks with gst-launch14:51
thaytanso it won't really work the same14:51
CarlFKthaytan: I was going to get to that in a bit ;)14:52
thaytanand you aren't setting matroskamux streamable=true14:52
thaytando you do that in the python script somewhere?14:52
CarlFKI dont think so14:52
mithrossk1328: It's a bit weird that the VTG deals with unpacking pixels, but I guess for now go with diagram P4?14:52
ssk1328mithro: Actual unpacking is being done in FIFO of driver if I am not wrong14:54
ssk1328mithro: Here https://github.com/timvideos/HDMI2USB-misoc-firmware/blob/master/gateware/hdmi_out/phy.py#L5414:54
tpbTitle: HDMI2USB-misoc-firmware/phy.py at master · timvideos/HDMI2USB-misoc-firmware · GitHub (at github.com)14:54
RattusRattusmithro: so C5VO1 datasheet is saying fit 2u2F ceramic you are now saying 22uF electrolytic..  thats fine (for bulk holdup on the rail) but you probably still want the ceramic in there as well for the low ESR to stop oscillation14:57
RattusRattusyou are saying that you are not sure fitting the recomended noise suppression caps on the PSU, but on the schematic you have warnings about noise on that PSU rail?  I am confused, why warn about noise sensativity and at the same time don't fit the the very thing that will improve the noise figure?14:59
RattusRattus^^ point 615:00
mithroRattusRattus: Trade offs right - adding 0402 capacitor is not a great idea on a board which is suppose to be hand solderable15:01
RattusRattuspoint 9 - this will never be a comercial grade device without them.....  its your call.  I would always fit them (but then I'm usuly the person called in to fix EMC issues on kit that fails EMC15:01
RattusRattusmithro: rarther like defensive programming I try and adopt a defensive PCB stratagy.  you can always not fit a part, it is much harder to fit a part if there isn't a space on the board for it....15:03
mithroRattusRattus: Adding ~20 resistors which means an extra ~400 parts to hand solder means it won't happen15:05
RattusRattusbut if you have stong feelings that you shouldn't do this then I am not going to fight over it.  I have given my recomendations and will try and be supportive whatever your decision.  I am happy to contribute even if the result is yes we looked at that and have decided not to implement it.  the point is it has at least been considered.15:05
mithroRattusRattus: If it was being machine built / commercially built, you might convince me15:06
RattusRattusare the opsis borads hand built?15:06
mithroRattusRattus: No15:06
RattusRattusok.  what if I were to do the hand soldering?  :-)15:07
mithroRattusRattus: well, more hand built then a 10k factory15:07
mithroRattusRattus: but still using a pick/n/place and stuff15:07
RattusRattusack - product is not 100% machine built15:07
mithroRattusRattus: I'm still skeptical of adding resistors to high speed lines - the pads + resistor muck with your impedance matching15:08
RattusRattus(/me has worked on 100k+ volumes and also 10 PA volumes so is aware of both production environments)15:08
mithroThe Opsis is done in batches of ~20 units if I understand correctly15:09
mithroThe current batch of VGA boards were hand soldered by rohitksingh in his bedroom if I understand correctly :P15:09
mithrowith what looked like a terrible soldering iron from the pictures15:10
RattusRattusre series termination - shouldn't have any effect on impeadance matching, it does make length matching a little more complex I admit, but you only have to add the length of 2 traces togeather15:10
mithroRattusRattus: impedance is control by things like the width of the trace, right?15:11
mithrossk1328: So I think we are better off converting to pixels earlier on in the pipeline because most things need to work with pixels15:11
RattusRattusyes, and distance to adjacent tracks, height over ground etc.15:11
mithroThe SMD resistor pads (and the resistor itself) is a giant discontinuity in that15:12
ssk1328mithro: So I guess, I should do the P4 diagram now15:12
mithrossk1328: Yeah - go with the P4 diagram if you think it's going to get you finished sooner - I do think we'll need to eventually refactor to P2 after GSoC15:13
* RattusRattus rolls over laughing 'impeadance' in this case is the effective charicteristic of the transmission line. the input you are driving will effectivly be open circuit (severl meg) adding 30 or 50R to that will make little or no differance, but will reduce amplitude of reflected signals massivly.15:15
RattusRattushence the series termination being good for EMC but not really effecting the transmission line itself15:16
mithroRattusRattus: If my trace needs to be 5mil width for 50 Ohm, and you make the trace 20mil - it's going to have a very different impedance right?15:18
mithroRattusRattus: The resistor pad is a short 20mil wide trace.15:18
RattusRattusyes.  so I have 96mm length transmission at 5mil and 4mm at 20 mil there is a differance but this is no where near as bad  as 100mm all at 20mil...15:20
RattusRattusat which point you are gaining more by having the resistor reduce reflection than you lose by the short length of incorrect impeadance.15:21
RattusRattus(which btw is true of the IC & connector footprints as well)15:21
RattusRattusanyway you have said that you are not interested in series termination.  so lets move on.15:23
mithroRattusRattus: This is the type of thing I'm talking about -> http://www.ti.com/lit/an/slla324/slla324.pdf15:23
mithroRattusRattus: I guess maybe it is because I'm working in a different domain here15:25
mithroAnyway - if you are offering to do the construction (and will actually do it) then you get to say if there are series resistors15:27
mithroPeople doing the work get to make the choices :-P15:27
mithroRattusRattus: I'd like to understand point 1015:28
RattusRattusmithro: (1) so this is looking at ESD protection in a transmission line (indeed I state in points 17 and 19 there should be ESD protection).  it then goes on to compensate for the effect of introducing the IC package to the charicteristic impeadance by using 'skinny' lines to balance out the effect.  nice.15:29
RattusRattus(2) the same technique could apply to series termination - only there is no signal (at least not enough) after the resistor to make any effect15:30
RattusRattusmithro: if hand placing then yes I can assemble.  logisticly I know that of your estimated 10 boards I would end up with 3 of them any way so I guess that makes sence15:31
mithroRattusRattus: I would probably do ~20 boards with the expectation of getting about 15ish that works reliably15:31
RattusRattusmeh that would still make the 3 for Debian a significant fraction of the boards.15:32
RattusRattusre point 1015:32
RattusRattusthe datasheet talks about there being high ripple current (i.e. big noise source) on the V_DD net (driving the digital RGB bus).  thefore filtering this power domain, and keeping it as small as possible is advantagous in reducing noise emmission15:34
RattusRattusthe ferite adds some degree of isolation from this power domain to the parent domain (main 3V3 rail).  Selecting a ferite to be as high impeadance as possible to the clock frequency you will use on this bus means that you get the effect at the point where you begin to need it.  in all probability the impeadance will still be rising at higher frequencies as well, but this is the first frequency that15:38
RattusRattus needs to be 'snubbed'15:38
mithroRattusRattus: So, I think I'm still missing something here15:47
RattusRattusright now that poer domain is directly connected to the main 3v3 rail.  you don't want that rail acting as an antenna and then back coupling into your sensative analogue signals15:48
mithroRattusRattus: can you do a diagram of (21)? Or even better add it directly to the schematic :P16:07
CarlFKthaytan:https://github.com/CarlFK/voctomix-outcasts/blob/master/tests/mock-stack.sh   I think it worked, but it is back to erroring http://paste.ubuntu.com/22814309/16:09
tpbTitle: voctomix-outcasts/mock-stack.sh at master · CarlFK/voctomix-outcasts · GitHub (at github.com)16:09
RattusRattusI think you miss understand my comment on point 20.  the IC has an internal weak pull down an A0.  it will default to A0 = 0.  adding an external pullup will make A0 = 1.  therfore there is never any need to fit a pull down....16:10
RattusRattusmithro: want me to addin ESD as well?16:11
mithroRattusRattus: I was looking at your suggested IC16:11
* RattusRattus has used the TI part before but not the other16:12
mithroRattusRattus: it looks like it might be cheaper then the I2C level shifter16:12
mithroLooks like http://www.digikey.com/product-detail/en/on-semiconductor/CM2009-02QR/CM2009-02QROSCT-ND/2442764 might be an alternative16:12
tpbTitle: CM2009-02QR ON Semiconductor | Circuit Protection | DigiKey (at www.digikey.com)16:12
RattusRattusyep.  looks fine16:13
RattusRattuslooks pin compatible with the Ti parts as well.16:15
mithroRattusRattus: I've pushed the latest changes to git16:17
RattusRattuscool will download this evening, and add the 5V VGA bit16:17
mithroat some point I have to do the IO pin changes16:18
RattusRattuswant me to addin the VGA ESD filter too?16:18
mithroRattusRattus: I wouldn't object16:18
RattusRattusand the SP724AHT?16:19
RattusRattusDon't wory about pin swapping - do that during PCB layout16:19
mithroRattusRattus: KiCad doesn't have a nice way of doing pin swapping16:20
mithroRattusRattus: so the PCB person sent me a list of her suggestions which I have to do manually16:20
RattusRattus:-)  yep.  swap and itterate, I remember those days16:21
RattusRattusare you paying for board layout?16:21
RattusRattusor is she doing it free16:21
mithroDoing it for free, she's retired and looking for something to do I believe16:22
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RattusRattus:-) great (/me would have done it to save you paying otherwise)16:23
mithroRattusRattus: well, I have a bunch of other boards I need done :-P16:24
RattusRattusI am concerned about #12 though.  you state "DATACK is bidirectional. Either the FPGA or the AD9984 can supply the data16:24
RattusRattusclock signal.but the datasheet states "This is the main clock output signal used to strobe the output data and HSOUT into16:24
RattusRattusexternal logic16:25
RattusRattusso you are going to have a problem there16:25
* RattusRattus is happy to route OH PCBs16:25
thaytanCarlFK, not sure, but if you start the sender before the receiver, the receiver might not get all the data?16:25
thaytanmissing the first part of a matroska file, even a streamable one, isn't good16:25
CarlFKah right16:26
RattusRattusmithro: I havn't found how to make that output Hi-Z in the datasheet16:26
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mithroRattusRattus: maybe I'm confused with a different AD part16:27
mithroRattusRattus: The FPGA pin can be set as In, Out or BiDir16:27
RattusRattuslol - this is the only potential show stopper :-)  as long as you only ever use the FPGA as IN then no issue, but if you want to drive from the FPGA as well then we need to add in a buffer with high-Z on dissable16:29
mithroRattusRattus: hrm? If the AD part doesn't support driving DATACK, then we don't make the FPGA do that :P16:31
mithroRattusRattus: oh, the FPGA can put its pins in High-Z too16:31
RattusRattusOOOOH!!! of cause we also need to check power on / reset states of IO lines from the FPGA to here as well.  if any default to output that will later be used as an input then that is a VERY good reason to include series termination...16:31
mithroRattusRattus: we can control what they are during power on / reset - I believe its currently configured as high-z16:32
RattusRattusmithro: the AD part always drives the DATACK line.....  it was you suggesting that you may want to drive that from the FPGA that has me worried16:32
RattusRattusreset power on as Hi-16:33
RattusRattusZ is always the safest16:33
RattusRattusthat clock is the dot clock from the AD part to the FPGA.....16:33
mithroRattusRattus: I was sure that it had a way to source the dot clock from the FPGA instead - but that must be a different part16:34
RattusRattusEXTCK/COAST This pin has dual functionality.16:35
RattusRattusEXTCK allows the insertion of an external clock source rather than the internally16:35
RattusRattusgenerated, PLL locked clock16:36
RattusRattusbut that is for analogue signal16:36
mithrorohitksingh is the expert anyway16:36
RattusRattusttfn - will update schematic tonight16:37
mithroI'm about to go to bed16:37
mithroas soon as CI provide I can merge this change16:37
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