Friday, 2016-07-29

*** tpb has joined #timvideos00:00
*** Bertl_oO is now known as Bertl_zZ01:21
*** sb0 has joined #timvideos01:59
*** CarlFK has joined #timvideos03:02
*** ChanServ sets mode: +v CarlFK03:02
mithroxfxf: ping?03:35
xfxfmithro: pong.  haven't progressed much this week due to day job taking up most of my awake time, working all of this w/e on AV things03:37
xfxfwill you be around?03:38
mithroxfxf: I hope to be, but no guarantees03:38
xfxfthat's fine03:38
*** nueces has joined #timvideos04:34
mithrossk1328: ping?04:42
nuecestoday I connected the hdmi output from my computer to the opsis, input 004:50
nuecesthe xrandr found it, but the opsis don't get any input04:51
tpbTitle: dpaste: 0YZGBPM (at
nuecesany ideas?04:52
mithronueces: what does the debug output show?04:52
mithronueces: what type of cable are you using?04:52
nuecesmithro, could you remember me how to use the debug?04:53
mithronueces: IIRC "debug input0" ?04:53
tpbTitle: dpaste: 0X2VKVZ (at
nuecesthe cable is not powered04:54
mithroThe WER is the problem04:55
nuecesmithro, it should be zero?04:59
mithronueces: It won't be until after PyCon AU before we add a bunch of stuff which will help you figure out the WER problem04:59
nuecesother thing the gnome display tool show the board as a OHW 9"04:59
mithronueces: Hrm?05:00
mithronueces: got a screenshot?05:00
ssk1328mithro: pong05:03
mithrossk1328: So, were are we at?05:04
ssk1328mithro: This week's report (not very complete) added on the doc05:04
mithrossk1328: yes, I had a read of it05:04
ssk1328mithro: I addded a video of dynamic fade I omplemented05:04
nueces(i connected a second input now, as it show in the console)05:04
mithrossk1328: Yes, I saw - looks pretty cool05:05
ssk1328mithro: Yeah! First output of my own mixer :)05:05
mithrossk1328: Is this the "two input / one output" type structure as in ?05:05
tpbTitle: Mixer Block Design - Google Docs (at
mithrossk1328: I realise now that we should have concentrated on this side first and left the RLE stuff till after this was working05:06
mithronueces: It is worth using xrandr --xprops to look at the edid and see what is there05:06
ssk1328mithro: yeah!05:07
ssk1328mithro: I have implemented the two input / one output type structure05:07
mithrossk1328: What needs to be done to fix the timing problem?05:08
nueces--xprops is an unrecognized option05:09
tpbTitle: dpaste: 0QWEDJQ (at
ssk1328mithro: I am not really sure, may need to run some changes in the gateware code05:11
ssk1328mithro: Maybe incorrect implementation of ack or stb somewhere05:11
mithronueces: That EDID block seems weird05:12
ssk1328mithro: Did you see the pics?  Maybe you could have seen something like that before?05:14
nuecesI'm going to use the prebuild firmware and back later05:14
mithrossk1328: Yes, I've seen that style of thing before05:15
ssk1328mithro: So you might know the exact reason why this happens?05:16
ssk1328mithro: As in the exactly what kind of timing issues05:16
mithrossk1328: There are a number of different causes05:16
nuecesmithro, this is the version that I'm using now05:16
tpbTitle: dpaste: 1G7M5DD (at
mithrossk1328: I think it occurs when the pixel data is being delivered at the wrong time05:18
mithrossk1328: but it could also mean the hsync/vsync signals are being sent incorrectly05:18
ssk1328mithro: Okay!05:18
mithrossk1328: It could be something like changing the frame buffer pointer at the wrong time05:19
ssk1328mithro: Also both the outputs (both the inputs of mixer block) aren't in sync with each other05:19
mithrossk1328: _florent_ might be able to show more insight05:19
mithrossk1328: Sure - the frame buffer helps you fix that right?05:19
ssk1328mithro: As in they are lagging by different times05:19
mithrossk1328: Yes the inputs are going to be offset from each other in time05:20
mithrossk1328: but they should be writing frames into the memory05:20
mithrossk1328: so you can read the two buffers from the memory in sync05:21
ssk1328Yeah, so I was reffereing to the output at memory before mixer block05:21
ssk1328mithro: Which are input to mixer block05:21
ssk1328mithro: They  arent in sync as seen in the pattern pic as well05:21
ssk1328mithro: You stop two different HDMI2USB texts05:22
mithrossk1328: Hrm?05:22
mithrossk1328: How are you feeding this?05:23
ssk1328*spot, not stop05:23
mithrossk1328: Are you using two DMA engines to get the memory buffers out of memory?05:23
ssk1328I added my modules in the output video pipeline05:24
tpbTitle: HDMI2USB-misoc-firmware/ at float-arithmetic · ssk1328/HDMI2USB-misoc-firmware · GitHub (at
mithrossk1328: The lines around 305 could be the cause of the alignment problem05:26
mithrossk1328: I don't get how you are getting two pixels into this?05:27
ssk1328mithro: Yeah so I add some more code in and call each of hdmi_out0 and hdmi_out1 class05:27
tpbTitle: HDMI2USB-misoc-firmware/ at float-arithmetic · ssk1328/HDMI2USB-misoc-firmware · GitHub (at
mithrossk1328: Okay, so it looks like you are just connecting both hdmi outputs together here05:30
ssk1328mithro: Yeah, I am putting the mult outputs of both the hdmi blocks into two of the add input05:31
mithrossk1328: So looking at
tpbTitle: HDMI2USB-misoc-firmware/ at float-arithmetic · ssk1328/HDMI2USB-misoc-firmware · GitHub (at
mithrossk1328: We need to split the DMA and Driver parts05:33
ssk1328mithro: Okay, we are doing this for solving the alignement problem right?05:34
mithrossk1328: We need the two DMA modules to deliver the same pixel value to the Driver at the same time05:35
ssk1328mithro: Okay, so instead of taking the second pixel stream from output1, I will add a nother DMA port at output0 and take the second pixel stream for mixer from there05:37
mithrossk1328: Yes05:38
mithrossk1328: I'm just wondering how you keep the two DMA engines in sync05:38
ssk1328mithro: Another thought, In the final version If I have all the outputs running then we should have 4 DMA ports instead of 2, demanding double the bandwidth, do we have such kind of available bandwidth?05:39
mithrossk1328: I think we want a single "FrameInitiator / VTG" module which two DMA ports are slaved too05:39
mithrossk1328: We only have 3 possible inputs, so we only actually need 3 possible DMA engines05:40
ssk1328mithro: Okay, so the bandwidth remains the same05:41
mithrossk1328: Notice in the "Three input, 2 output" we have 3 DMA inputs05:41
ssk1328mithro: Yes05:41
mithrossk1328: I added some extra stuff to the diagram just then05:44
mithrossk1328: I think it kind of works like this...05:44
ssk1328mithro: Just looking at it05:45
mithrossk1328: I think the FrameInitiator is what generates the in-memory address for each pixel?05:45
ssk1328mithro: Yeah, the csr functions also have a fi in them05:46
mithrohrm - the FrameInitiator seems to be connected to the VTG05:48
ssk1328Yes, and then VTG to Driver05:50
mithroso it seems that the FrameInitator and DMA both feed into the VTG which then feeds the output driver...05:50
mithroDon't know if it is a feed or pull structure though....05:50
mithrobe back in 30 - meeting05:50
ssk1328mithro: Okay05:52
*** aom_ has joined #timvideos06:11
*** springermac has quit IRC06:12
*** aom_ has quit IRC06:24
nuecesmithro, in all the cases the display is detected as OHW 9", the edid seams to be the same for the unstable/testing/stable prebuild firmware06:31
tpbTitle: dpaste: 1VZ4793 (at
nuecesmithro, there is a updated list of know cameras that works with the board?06:31
nuecesthanks and god night (time to sleep for me)06:32
mithronueces: Someone needs to work on the EDID a bit I think06:33
*** springermac has joined #timvideos07:14
*** Bertl_zZ is now known as Bertl08:28
*** CarlFK has quit IRC14:19
*** danielki has joined #timvideos14:40
*** CarlFK has joined #timvideos14:41
*** ChanServ sets mode: +v CarlFK14:41
*** CarlFK has quit IRC14:58
*** ssk1328 has quit IRC15:55
*** Bertl is now known as Bertl_oO15:55
*** aom has joined #timvideos16:34
*** ssk1328 has joined #timvideos16:53
*** CarlFK has joined #timvideos17:18
*** ChanServ sets mode: +v CarlFK17:18
*** CarlFK has quit IRC18:39
*** CarlFK has joined #timvideos18:49
*** ChanServ sets mode: +v CarlFK18:49
*** ssk1328 has quit IRC18:55
*** danielki has quit IRC19:54
*** aom has quit IRC20:14
*** nueces has quit IRC20:32
*** danielki has joined #timvideos21:46
*** Bertl_oO is now known as Bertl_zZ22:23

Generated by 2.13.1 by Marius Gedminas - find it at!