Wednesday, 2016-07-27

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tumbleweedmithro: so now, I have a logic analyzer. But I don't know what I'm doing with it04:34
tumbleweedand can't find the UART on the TOFE pinout in the opsis docs04:35
mithrotumbleweed: You want to attach the logic analyzer to the I2C bus and reset line between FX2 and the FPGA04:40
mithrotumbleweed: one problem you have is that the I2C CLK isn't on a header anywhere04:42
tumbleweedI'll need some help finding it04:46
mithroUMAC1 is probably the best IC to use04:55
mithrotumbleweed: Look at the schematic do at and page 7 you can find the UMAC1 wiring04:56
tpbTitle: HDMI2USB-numato-opsis-hardware/Numato-Opsis-v3-prod-3-g83e7bd5.pdf at master · timvideos/HDMI2USB-numato-opsis-hardware · GitHub (at
tumbleweedU23 is nice and big, so I'm giving it a shot04:58
mithrotumbleweed: yeah04:59
mithroSDA signal is also avaliable on P1805:00
mithroThe reset signal is available on K3 == JFX2-RST05:00
tumbleweedtrying to figure out how external clock is supposed to work05:07
mithrotumbleweed: hrm?05:11
tumbleweedhow do I get it to use the I2C bus' clock?05:14
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mithrotumbleweed: You just want to capture the clock + data signals?05:18
mithrotumbleweed: So you need to attach your logic analyzer to pins 5 and 6 of UMAC105:26
tumbleweedyeah, I gave up on external clock, and just captured at a higher clock rate05:29
tumbleweedI have some analysis which is basically a screen full of bus errors05:30
mithrotumbleweed: oh, yeah you definitely want to oversample it05:30
mithrotumbleweed: you also want to trigger on the JFX2-RST05:30
tumbleweedaha, let's try that05:31
tumbleweedJFX2-RST seems to stay high a lot05:33
mithrotumbleweed: That is expected, the FX2 is only running when it is high IIRC05:34
mithroyou pull it low to reset the FX205:34
tumbleweedthat's annoying for triggering05:34
mithrotumbleweed: you want to trigger on it going high05:35
mithrotumbleweed: the SDA and SCL should be idle for the rest of the time05:35
mithrotumbleweed: but just after a reset it will read a bunch of stuff out of the EEPROM first, and then from the FPGA second05:35
* tumbleweed was getting data before, now all the pins just seem to be high :/05:41
mithrotumbleweed: The data will only occur after a reset05:41
mithrossk1328: ping?05:45
tumbleweedmithro: no, I mean, the clock line is just staying high now05:55
* tumbleweed is confused05:55
mithrotumbleweed: the clock line will only toggle when it is sending data05:55
mithrotumbleweed: Do you know how I2C works?05:56
tumbleweedwell it's serial, so yes, that's what I'd expect05:56
tumbleweedbut that's not what's happening05:56
tumbleweedwhich is why I'm confused05:56
tumbleweedI don't know the I2C protocol05:57
tumbleweedbut I do know that these logic lines probably shouldn't be staying high05:57
tumbleweedaha, because I'm being a numpty06:00
tumbleweedwell that was obvious06:00
tumbleweedbut you know...06:00
mithrotumbleweed: When idle, they will remain high06:05
tpbTitle: I2C - (at
tumbleweedno, there seems to be a bug in this software06:06
tumbleweedif you use too big a capture buffer, it's all corrupted06:06
tumbleweedI noticed this earlier06:06
ssk1328mithro: Pong06:09
ssk1328mithro: did you see the doc I sent here06:09
mithrossk1328: yes06:09
mithrossk1328: I don't quite understand the first section06:09
ssk1328mithro: that's a problem I am unable to solve06:10
mithrossk1328: You can have multiple sinks in a component06:10
mithrossk1328: Why doesn't the adder block just have two sinks?06:11
ssk1328I tried that06:11
ssk1328mithro: That gave a error06:11
ssk1328Maybe not using the correct way06:11
mithrossk1328: What was the error?06:11
ssk1328mithro: Let me reproduce, but it was something about Endpoint can't have two definition of sink06:13
tumbleweedmithro: also (FX2-RST seems to be having some fun)06:14
mithrotumbleweed: Okay, lets start with FX2-RST - the correct behaviour is that on boot it goes high, then at some point later it will get pulled low for a period and then go high again06:15
tumbleweedit is rather wobbly06:15
tumbleweedit's line 2 in my capture06:15
mithrotumbleweed: That is the FPGA resetting the FX2 to get it to read the new firmware06:15
mithroI dunno how to read a sla file?06:16
mithrossk1328: Can you give me edit access so I can play with your block diagram?06:16
tumbleweedmithro: with SUMP06:16
tumbleweedmithro: at 1.8ms, it seems to settle down06:16
ssk1328mithro: Sharing setting changed06:18
tpbTitle: HDMI2USB-misoc-firmware/fx2.c at master · timvideos/HDMI2USB-misoc-firmware · GitHub (at
tumbleweedwhen I say wobbly I mean it's toggling faster than the I2C clock, at times06:21
tpbTitle: HDMI2USB-misoc-firmware/ at master · timvideos/HDMI2USB-misoc-firmware · GitHub (at
mithrotumbleweed: It shouldn't be toggling....06:21
tumbleweedwell yeah, that's why I mention it06:22
ssk1328mithro: This is how am I doing it right now, and surprisingly no errors turned up06:26
tpbTitle: Ubuntu Pastebin (at
ssk1328mithro: I have started the make gateware for this, lets how this works out06:27
ssk1328mithro: Made a typo in above code06:31
ssk1328mithro: I am gonna pastebin the error I got here06:32
tpbTitle: Ubuntu Pastebin (at
ssk1328mithro: Also the correct code which cause this error
tpbTitle: Ubuntu Pastebin (at
mithrossk1328: That isn't an error?06:35
ssk1328mithro: The second pastebin is the terminal output of error I get06:37
tumbleweedmithro: I'm guessing it could just be a very slow transition from low to high06:37
tumbleweedbut there are still some spikes to low06:38
mithrossk1328: Ask _florent_ or in #m-labs06:42
ssk1328mithro: Okay06:42
mithrotumbleweed: It's hard for me to tell if the problem is actually your FX2 line or your equipment?07:04
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mithrossk1328: I updated your document with my thinking about the pipeline10:16
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tumbleweedmithro: I can't tell, either16:23
tumbleweedmithro: and it's not necessarily a problem. How did the rest of that I2C dump look?16:23
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ssk1328mithro: I saw the changes18:52
ssk1328mithro: I had a similar thing in mind18:53
ssk1328mithro: Though I need to figure out things for encoder as well18:53
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