Monday, 2015-11-09

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mithroCarlFK: The VGA board is mainly designed for VGA in rather then VGA in + VGA out04:49
CarlFKmithro: shucks04:49
CarlFKbut I can work around it.04:50
mithroNot enough spare pins I'm afraid04:53
mithrobtw I'll be spending next week working on the HDMI2USB firmware full time in preparation for the Opsis04:58
mithroysionneau: ping?05:41
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ysionneaupong!10:15
ysionneaumithro10:15
mithroysionneau: heyo! Did you get to the bottom of what is going on with the I2C stuff?10:16
ysionneauhi! I'm still in London (was in 0xford yesterday) and I didn't get the time to work again on it10:16
mithroysionneau: No worries10:16
ysionneauI'm wondering what's your deadline for this10:16
mithroysionneau: I'll be spending the time period from the 14th till 22nd working full time on building a production Opsis firmware (taking time off from work)10:17
ysionneauOk, for this week (starting tuesday) I don't have anything planned, so I will be available to work10:18
mithroCarlFK / tumbleweed: BTW That includes making it so that the Opsis boots up with the firmware without having to flash10:18
ysionneauso I will most likely update you on Tuesday about the stuff we talked about10:18
mithroysionneau: Your modified EDID part is a fallback option regarding getting booting working10:19
ysionneauok10:19
mithroysionneau: I also need to figure out a communication method between the Opsis and FX2 for transferring things like resolution settings10:19
ysionneaubecause this needs to be in the USB descriptor?10:20
ysionneauor something?10:20
mithroysionneau: I have 3 pins to work with on the Atlys<->FX2, have a lot more on the Opsis<->FX210:20
mithroysionneau: yeah10:20
ysionneau3 pins, can do something like SPI or I2C10:21
mithroysionneau: Yeah - but it'll have to be bitbanged :)10:21
ysionneau\o/10:21
mithroysionneau: The FX2 is pretty slow10:21
mithroabout ~12MHz10:21
ysionneauok10:21
ysionneauso it'll be best if the FX2 is the master of such a communication then?10:22
ysionneauit'll be bitbang on both sides? fx2 pins are regular gpios?10:22
mithroI can do roughly ~500kHz bit banging if doing nothing else10:22
ysionneauok10:23
mithrothe FX2 has a bunch of interrupts it needs to service, so I think it'll need to be the master10:23
mithrothis is separate from the I2C bus used for the firmware loading10:23
mithroThe big problem is the Atlys board10:23
mithroOn the Opsis I can use the I2C hardware, the hardware UARTs or an ~12 GPIO pins10:24
ysionneauyes ok so it'll need to be soem bitbanged protocole with fx2 as master for the Atlys board then10:25
ysionneausome*10:25
mithroyeah10:25
ysionneaustill have "plenty" of code space for the fx2?10:25
seaLnemithro: should the i2c bus for the ad9984 be seperate from the eeprom? the eeprom on the vmod is on the same bus10:25
mithronot a huge amount, but definately few 4-5kb10:26
mithroseaLne: nah, they can be the same as they are on different addresses10:26
mithroseaLne: but make sure they are :)10:26
mithroysionneau: I already have some highly optimised bitbanging code for doing JTAG programming using the FX210:26
ysionneauhehe ok10:27
mithroysionneau: another option is the trying to use the USB FIFO buffers to transfer data10:27
seaLnemithro: ok and yep. just wondered from an architecture point of view of tofe10:27
ysionneaumithro: hmm ok I don't know much about that10:27
mithroysionneau: I think it could work, but haven't had a chance to test it yet10:28
ysionneauthose buffers can be used for something else than USB?10:28
mithroysionneau: I can effectively "veto" the buffers going to/from the USB bus10:28
mithroIt's unclear if I can totally generate a buffer though10:28
mithroysionneau: We use sdcc for compiling the fx2 code10:29
ysionneauit does not seem to be in the default ubuntu repositories but I guess it's easy to install10:30
ysionneau?10:30
mithroysionneau: apt-get install sdcc10:30
mithroysionneau: we also have a newer version in conda10:30
mithroysionneau: It kinds of feels like there should be a kind of generic "i2c library" that we could share between the fx2/lm32/etc10:31
ysionneauthat would make sense yes10:31
mithroI'm kind of surprised something like that does already exist10:31
ysionneauLinux kernel has an i2c bitbanged driver10:31
ysionneaubut don't know if it's easy to strip all the kernel specific calls10:32
mithroysionneau: Thinking at the levels, first we have the low level "I2C UART" bits - which is either bitbanging or hardware assisted10:33
ysionneauI think it's this one http://lxr.free-electrons.com/source/drivers/i2c/algos/i2c-algo-bit.c10:34
tpbTitle: Linux/drivers/i2c/algos/i2c-algo-bit.c - Linux Cross Reference - Free Electrons (at lxr.free-electrons.com)10:34
mithroysionneau: the next level above that is kind of the protocol level, IE what to based on i2c bytes (IE only respond to things matching your address, etc)10:34
ysionneauyes10:34
mithroysionneau: then the next level up is the high level "eeprom reading protocol" and "ad9984 protocol" etc10:34
mithroI wondered if we could steal anything from sigrok - http://sigrok.org/wiki/Protocol_decoders10:38
tpbTitle: Protocol decoders - sigrok (at sigrok.org)10:38
ysionneaufrom a decoder, hmm10:44
mithroysionneau: anyway - I just wanted to mentioned where I was at10:55
ysionneauok, good to know!10:57
mithroBertl_zZ: could you generate me a BOMs (parts list) for the HDMI adapter, 3 x PMOD and PMOD test thingy? I don't have Eagle to open the schematic and I couldn't find PDFs for them at http://vserver.13thfloor.at/Stuff/AXIOM/BETA/ ?10:58
tpbTitle: Index of /Stuff/AXIOM/BETA (at vserver.13thfloor.at)10:58
ysionneauhave to go for lunch, see you!11:02
mithroysionneau: It would be good to know what is happening regarding the lm32 gpio bitbanging by Friday11:04
ysionneaushould be good11:06
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seaLnemithro: if the ad8944 uses the same i2c bus as the tofe eeprom won't then the tofe-vga and vmod-vga be incompatible as it uses IO20 for the i2c?11:29
seaLnewhich on the tofe is B33 and B3411:30
mithroseaLne: just a very small software change11:30
mithroseaLne: but there might be no reason to change it11:30
mithroseaLne: you using https://docs.google.com/spreadsheets/d/15rivtOcSG4kqKf0AUK_OwBfs67XQtW8byr8kc5FUTgE/edit#gid=574892795 ?11:30
tpbTitle: Tims Open FPGA Expansion (TOFE) board connector interface - Google Sheets (at docs.google.com)11:30
seaLneyes11:31
mithroseaLne: ahh cool11:31
seaLnejust keeping it the same seems like the easiest solution?11:31
Bertlmithro: http://pastebin.com/raw.php?i=SzxJEqbU11:51
mithroseaLne: sgtm11:51
BertlI'll see what I can do for the triple PMOD and PMOD debug11:51
Bertl(will take a little though)11:52
mithroBertl: just need a part list, not a farnell order number stuff12:14
Bertlhttp://pastebin.com/raw.php?i=rBTwgu1i (3xPMOD)12:31
mithroBertl: I don't quite understand what I should be looking for regarding the 2.54mm socket strip? It seems to be surface mounted in some way?12:34
mithroEverything else looks good12:35
Bertlhttp://pastebin.com/raw.php?i=1vkD7cp712:35
Bertlit is just stuck to the PCB and soldered on both sides12:36
Bertli.e. you get a normal header or socket strip with 2x6 pins/holes12:36
Bertlthen stick it on the PCB edge, align it and solder it12:37
Bertlse6astian: do we have a close up of the PMOD debug module somewhere? google doesn't find anything12:39
Bertlse6astian: same for the triple PMOD12:39
se6astiando you mean this: https://apertus.org/pmod-debug ?12:49
tpbTitle: PMOD Debug Board | apertusĀ° - open source cinema (at apertus.org)12:49
mithroBertl: ahh I understand12:50
mithroBertl: that is the same for the 3xPMOD stuff12:51
Bertlse6astian: well, I was hoping for a close up picture12:51
Bertlit seems we do not have any of either12:51
seaLnemithro: i think keeping the same pinout between the vmod and tofe vga may not be possible as on the tofe the RGB buses from the ad9984 would be criss-crossing all over the place making length matching a bit of a nightmare. the pins seemed to have been picked on the vmod as they were next to each other12:52
Bertlmithro: yes, triple PMOD is the same just the opposite gender12:52
mithroBertl: okay great12:52
mithroBertl: I just realised they aren't that much use without something to connect to them :P12:53
mithroseaLne: yes, feel free to swap LVDS pairs as needed12:53
mithroMy brain always reads MURATA as 'MURRICA12:54
Bertlmithro: that's what the PMOD debug module is for, i.e. you can plug in all three of them into the triple PMOD dual slot plugin12:55
Bertl(which in turn plugs into the mithro special TOFE-AXIOM adapter :)12:55
mithroBertl: yeah, but I need to finish that adapter first :)12:55
mithroBertl: the reason I was thinking about parts is I need to order the mDP connectors to test your theory about only fitting 3 of them on a board12:56
mithroBertl: If we can somehow fit 4, we end up with a nice feature that you can use 2 for a single width board12:56
Bertlyep, but won't work12:57
mithroBertl: so you could do a HDMI connector and a "half size link"12:57
mithroBertl: I assume everything need to be facing "upwards", IE we can't have things facing off to the sides?12:58
Bertlhttps://www.apertus.org/sites/default/files/PCB-Stack-Concept-V03-022b-transp.png13:00
Bertlso in theory, you can have something stick out to the (out)side as well, but that's not how it is designed13:00
mithrowe are also 1 pin short with 3xmDP :/13:03
Bertlhow so?13:04
Bertlor you mean, we have one spare low speed I/O? if so, then yes, we can leave that one unused or attach an LED13:05
mithroBertl: with 3xDP we can't connect one low speed I/O from TOFE<->AXIOM13:14
Bertlbecause the TOFE has only 2 DP with "low speed" connections, I know13:14
Bertlbut I wouldn't worry too much about that13:15
seaLnemithro: on the opsis is it only individual pairs that are length matched to the tofe connector? the ad9984 doesn't use pairs it has 3x 10 signals so i'm not sure how much use length matching on the vga board will be if they aren't then between the connector and fpga on the opsis?13:26
mithroseaLne: yes, they are all length matched IIRC13:26
mithroseaLne: but pairs are length matched and routed as a couple13:27
seaLneso between pairs they won't be the same lenght?13:27
mithroseaLne: they should be13:27
mithroseaLne: just tighter tolerances for matching a pair rather than the whole group13:27
seaLnemithro: ok, thanks13:28
mithroseaLne: we can also delay tune the IO in the FPGA if we can get the ad9984 to produce a known bit pattern13:28
seaLnethanks just trying to sort this out in my head13:30
mithroseaLne: I think we could basically fix almost any issue in the FPGA if you had the connections working - but some take more effort then others13:31
mithroBertl: the latest thoughts are in the TOFE spreadsheet - I was hoping to figure out a way to do the 3xmDP for AXIOM in a way that the 4xmDP  would still make sense for TOFE<->TOFE but don't see a way to make that'll end up working13:42
mithroanyway bed time for me!13:42
mithrognight!13:42
BertlseaLne: at 170MHz, the wavelength is about 1.5 meter (~60 inch), so the pair length is not _that_ critical :)13:48
Bertlmithro: no worries, just handle the TOFE-TOFE and we'll be fine13:49
Bertlmithro: and sleep well13:49
seaLneBertl: good point :)13:53
Bertlwhat I would avoid though is having different clock domains on the same pair, as the crosstalk will be significant on an impedance controlled pair14:03
seaLneBertl: will the RGB (10bit) not all be sent out at the same time? or were you more meaning don't share with the other things?14:12
Bertlyes, all the AD9984 outputs will probably be synchronous14:13
Bertlbut don't mix them with "other" clock or data lanes on the same pair14:15
seaLneyep, thanks14:15
Bertlnp14:15
seaLnedo i need to worry about where on the fpga the pairs go to?14:16
Bertlprobably not, but if you want to play it extra safe, I'd put them in direct vicinity (i.e. on the same bank(s))14:47
CarlFKleft my atlys runing over night.  I have fuzzy line on top of the test pattern15:20
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seaLnethat doesn't sound good15:42
BertlGTX tranceivers or normal output?15:44
Bertl(might be a problem with the timing closure under higher temperature)15:44
Bertlanyway, off for a nap ... bbl15:44
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CarlFKseaLne: bringing up a console now...15:52
CarlFKseaLne: hmm.. something odd is going on...15:54
CarlFK[FLTERM] Starting...15:54
CarlFKDIUB15:54
CarlFKit's like there is still a connection somewhere...15:54
CarlFKoh right, there is :)15:55
seaLnei guess things to test: does switching encoder on/off fix it. does power cycling fix it. does leaving it to cool down fix it?15:57
CarlFKoutput0: [email protected] from pattern15:58
CarlFKI started it about 9 hours ago, observed it for maybe 10 min and went to bed15:59
CarlFKwoke up, see fuzzy line.  which I have seen before, it is very distinctive, ... um.. know what I mean?16:00
seaLnehang over? :)16:01
CarlFKlol16:01
CarlFKI mean the line that shows up now and then16:02
CarlFKit runs down the middle of the white bar of the pattern16:02
CarlFKseaLne: ^^^ have you seen that before?16:11
seaLneCarlFK: nope sorry, not seen the atlys in use16:12
CarlFKseaLne: I would think it is a firmware thing, not hardware16:13
CarlFKbut im not sure what you have or do16:13
seaLnemy first 2 suggestions to test would probably point at firmware if they fix it. if it needs to cool down or never works again would suggest overheating. these are just some guesses i'm sure there are others with much more knowledge16:15
seaLnecould also be problems with the uvc driver on the pc?16:16
seaLneso possibly the first test could be unplugging the usb cables?16:17
CarlFKit is showing up on the hdmi display16:18
CarlFKoutput0: [email protected] from pattern16:18
seaLnewell ruled one thing out now16:19
CarlFKI have seen it on a black screen when there is no hdmi on the source, like if nothing was hooked up to input0, and output0: [email protected] from inpurt016:20
CarlFKthe explanation was "nothing is writing to the ram, so it is whatever data happens to be in ram"16:20
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