Monday, 2015-04-27

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mithroshenki: ping?05:17
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shenkimithro: pong05:24
mithroshenki: how are things? I'm guessing you've been pretty busy as I haven't seen you around here much05:24
mithroCarlFK: ping?05:27
CarlFKmithro: pong05:27
mithroCarlFK: I sent you some instructions in reply to your email. Do they make sense?05:27
shenkimithro: yeah. I'm in Canberra for the second time this month, this time for 10 days05:31
mithroshenki: well, if you ever want to pop down to Sydney, you are always welcome to crash on my couch (assuming nobody else is using it :)05:33
shenkimithro: thanks :) I considered trying to make it part of the trip, but i didn't work out this tim05:34
shenkithis time05:34
shenkimithro: next trip i'll make sure i come over for a day or two05:35
shenkimithro: what's new with you?05:35
mithroshenki: if you wanted to take a day off on a Monday or Friday, I would love to take one off too05:35
mithroshenki: personal wise, not much05:36
mithroshenki: project wise - been playing with misoc/migen from the #m-labs guys, getting very close to sending the rev2 board off for prototyping05:36
shenkivery cool05:37
shenkimithro: what have you got migen doing?05:37
mithrothe main reason I'm interested in the misoc/migen stuff is they have a bunch of fully open cores for things like DDR, Ethernet, PCI-Express which works across a wide variety of FPGAs05:39
mithroIE Spartan 6, Atrix (such as in the Zynq), etc05:40
shenkicool. so it makes us less dependant on the IDEs and IP provided by the vendors05:44
mithroshenki: yes05:44
shenkieasier to run the same firmware across multiple famlies05:44
mithroif we want to support Zynq and Novena, misoc seems like a good option05:45
mithroCouple of downsides05:45
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mithroSet up is a lot harder than just install the Xilinx tools, it requires a custom compiled gcc+binutils because they do the RAM initialisation using a CPU softcore05:46
mithroMost of their cores is written in migen, which has a much smaller user base then vhdl / verilog05:47
mithroBut migen is much nicer than raw vhdl / verilog in many ways - not as nice as cfelton's myhdl05:48
mithroThe only missing parts in misoc which we need for a HDMI2USB are our custom USB stuff and a mjpeg core05:48
shenkiyou can still integrate with vhdl cores?05:48
mithroshenki: yes05:48
CarlFKmithro: instructions - I think so.05:49
mithroCarlFK: please attach anything you managed to collect to that bug05:49
CarlFKmithro: is the i2c timing controlled by the fpga code (or whatever it is called)  something we control, or is it built into the atlys board?05:50
mithroshenki: Carl's email about reminded me that I've been meaning to catch up with you :)05:50
tpbTitle: Debug unreliable screen detection and possible EDID issue · Issue #105 · timvideos/HDMI2USB · GitHub (at
mithroCarlFK: IIRC the laptop controls the clock for the EDID I2C05:51
shenkimithro: yeah. i'd like to find some time to spend on that05:51
mithroshenki: yeah - I should spend some time looking into it too05:51
CarlFKmithro: but does the fpga lookto the i2c clock and form the data bit signal?  (which seems the only way this would be broken)05:53
CarlFKI would expect the i2c protocol to be implemented in support chips. but yeah, I don't really know what I am talking about :p05:54
mithroI think shenki knows the details about the i2c stuff better than myself05:55
mithroThe basic idea is that the laptop will send some commands to the FPGA saying "please send me the EDID data" which the FPGA then response too.05:55
mithroThe FPGA is basically pretending to be an EEPROM memory device.05:55
mithroSo there could be a bunch of things going wrong05:57
CarlFKI was told "sound like the i2c communication isn't done right.  a scope might show that."    which surprised me05:57
mithroThe scope will give you the "raw data" for what is being sent / received.05:57
mithroWhich you can then decode into the I2C commands / responses.05:58
CarlFK"the bits might not be aligned with the clock, or they may not be square enough, they could rise from 0 to 1 in a slope that is out of spec."05:59
shenkiwe captured that, in the failure case, and it appeared to be fine05:59
mithroshenki: I don't think we trust our capture device in that case, right?05:59
CarlFKah.  yeah.  I suspect this is from historic problems building i2c from scratch, not build into a board like the atlys.05:59
shenkimithro: yeah. not enough to write it off, but it is evidence that the hypothesis is wrong06:00
CarlFKbut don't worry, Ill go down this path- it's easy enough for me.06:00
shenkii suspect it's due to a lack of integrity in the presence signal06:00
shenkiso the device keeps on re-appearing to the host06:00
mithroCarlFK: those are all low level things which could cause the I2C signal to be wrong06:00
shenkithat issue is compounded by our all of testing being through HDMI/DVI -> DP06:01
shenkiso we introduce someone else's chipset to the mix06:01
mithroshenki: each time a "reappearing" occurs there should be a new set of I2C communication, right?06:01
mithroCarlFK: if the signal timing / levels / etc are wrong then the data is probably not getting through correctly06:02
CarlFKmithro:  sounds like things that would have been designed and implemented by Digilent Atlys devs and manufacturing, not the fpga code.06:02
mithroCarlFK: no, that is the point of an FPGA - this is done in software now instead of hardware06:02
CarlFKk, that's what I wasn't sure of06:03
mithroCarlFK: otherwise we couldn't customise it06:03
shenkimithro: right. but that could be all kinds of confusing to any of the systems in chain - FPGA, adapter, PC - if we're strobing the connection line06:03
mithroshenki: we don't actually have control over the HPD line on the Atlys board, it is hard wired06:04
shenkimithro: yeah06:04
mithroCarlFK: btw can you describe the unreliable setup you have?06:04
shenkimithro: we can still scope it, see what the signal integrity looks like06:04
mithroshenki: yeah06:04
mithroshenki: much harder to scope though :(06:04
mithroCarlFK: does your scope friend have a github account?06:05
CarlFKmy "LENOVO ThinkPad Twist 33474HU" laptop (that I do all my dev on) has a display port and a mini hdmi.  DP -> htmi dongle ->atlys works fine.06:07
CarlFKmini hdmi -> atlys, about 50% of the time xrandr shows the correct res06:07
CarlFKwatch xrandr shows it fliping between good and not good values, including xrandr segfaulting06:08
CarlFKI haven't been able to capture not good06:08
CarlFKalso, even when not runing xrandr over and over, after the first one, I see syslog detecting  a new hdmi device every second or two.    but that may just be ubuntu hot plug going wonky.06:10
CarlFKand my cpu load goes nuts and things get very unresponsive, which makes it hard to gather stats06:11
CarlFKmithro: scope guy is a ps1 member that I don't really know.   someone else knows he generally brings it to the SOC meetings every two weeks06:14
mithroCarlFK: on a related note, one thing which would be useful to research EDID information and decode what is actually in our EDID hex blocks06:14
mithroCarlFK: our EDID block might be technically valid but actually unusual in some way which Linux doesn't like06:15
CarlFKgood news: this scope has a bunch of protocol decoders, so it should be able to dump that in human readable or maybe even to a usb stick or something wonderful06:16
mithroCarlFK: please try and get the raw trace values too06:18
mithroCarlFK: but most scopes have a way to dump that data to something like a CSV or similar file06:18
CarlFKmithro: the NERP meeting starts at 7, I expect 8:30 will be when it breaks and Andrew will start probing the i2c stuff.  I'll ping you here on IRC.  I expect he will know what sorts of things will be useful06:24
mithrowhen is this?06:25
CarlFKin about 18 hours06:29
CarlFK20:30 - 1:30 now = 19 hours06:30
mithroCarlFK: okay, I'll try and be around - but don't know if I will06:41
CarlFKI suspect in 2 weeks I'll have a hdmi break out and do another ... scoping06:56
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MaZderMindso, back from a sunny weekend.08:13
MaZderMindCarlFK: "if you needed to record something next week, would you use dvswitch" - it depends. For a conference and if they don't have hardware mixers present: yes. For Single-Talks we're experimenting with recording slides and cam in parallel and mix them during the final encoding :08:15
MaZderMindCarlFK: "if you needed to record something next week, would you use dvswitch" - it depends. For a conference and if they don't have hardware mixers present: yes. For Single-Talks we're experimenting with recording slides and cam in parallel and mix them during the final encoding:
MaZderMindCarlFK: mithro did you try the Epiphan EDID-Files? They have a collection of various EDID-Blobs to use:08:23
tpbTitle: DVI2USB 3.0 downloads (at
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MaZderMindused the weekend to get into vhdl:
tpbTitle: mazdermind on Twitter: "When I look at it, my bench looks nearly as crowded as @eevblogs. time to hire… no. to clean up." (at
MaZderMindslowly getting used to it10:50
mithroMaZderMind: if you wanted to take a look at too, it can't hurt to have more traces.10:51
tpbTitle: Debug unreliable screen detection and possible EDID issue · Issue #105 · timvideos/HDMI2USB · GitHub (at
mithroMaZderMind: At the moment changing the edid hex files requires recompiling the firmware10:52
mithroMaZderMind: I realise now that we should have some way to dynamically load the EDID data10:52
mithroMaZderMind: there are instructions on the issue about what / where to capture stuff10:57
MaZderMindmithro: i'll take a look at it when I'm ready to10:57
MaZderMindstill learning fpgs-basics, I want to build my own view on how things work instead of just probing & guessing around10:58
mithroMaZderMind: no worries11:02
mithroMaZderMind: if you have questions, please do feel free to ask here - even if it's just general FPGA questions11:02
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CarlFKMaZderMind:  my point is you wouldn't use gst-switch13:21
MaZderMindCarlFK: no, because there are some unsolved problems that makes it unusable in our setup:13:30
MaZderMind for example13:31
tpbTitle: GUI<->Server via GBit Ethernet · Issue #111 · timvideos/gst-switch · GitHub (at
MaZderMindCarlFK: but I hope to get the blockers solved over the year and to have gst-switch as viable solution for autumn and the coming year13:31
MaZderMindCarlFK: we have a whole lot of conference to play at:
tpbTitle: Start [CCC VOC] (at
CarlFKMaZderMind:  I think this should be one of the easier fpga tasks
tpbTitle: Map 720p and 1024x768 to a hardware switch · Issue #102 · timvideos/HDMI2USB · GitHub (at
CarlFKMaZderMind: I think timvideos/gst-switch can be used sooner.13:53
CarlFKit just needs to function like dvswtich v.6 or whatever version they first used. no pnp, no fade, just switch between streams13:54
mithroCarlFK: have you tried that recently?13:57
CarlFKjust ran it.  I don't see anything new14:00
mithroCarlFK: what is missing from switching between streams in that UI?14:04
MaZderMindthe blocker for the VOC testing gst-switch in production are the #102 (srv <-> ui via ethernet) and that possible memleak14:07
MaZderMindbut I planned on doing it right: fix the tests, rewrite the GUI and *then* work on the missing server parts14:07
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CarlFKsorry folks - ran it with 2  test streams and my CPU meeter pegged then froze and I had to power cycle14:14
mithroI need to head home14:19
MaZderMindnight mithro14:21
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skaymithro: Carl is rebooting14:23
skayI'm busy14:23
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CarlFK1ok, no more running anything but irc14:24
CarlFK1last time I tried to do some testing, I realized I couldn't figure out how to operate it14:25
CarlFK1I ended up with a 2nd laptop with docs open in a window14:26
CarlFK1and bouncing between the docs and the UI for a few min didn't seem to be training my memory14:26
CarlFK1mithro: did I loose you?14:30
cfeltonCarlFK1: yes, I believe mithro left14:33
CarlFK1MaZderMind: can you clone and run
tpbTitle: dvsmon/ at master · CarlFK/dvsmon · GitHub (at
CarlFK1either clone it in the right place or change PATH="`pwd`/../gst-switch/tools:$PATH"14:41
MaZderMindCarlFK1: seems an -f is required on the server (my defaults may be different)14:49
MaZderMinddespite that it runs quite nicely14:49
CarlFK1ah right.  what's the -f I need to work with my test streams ?15:01
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MaZderMindCarlFK1: well it just needs to be the same for sources & server, see
tpbTitle: gst-switch/ at master · timvideos/gst-switch · GitHub (at
CarlFK1oh neat I didn't realize it would take gstreamer .. um.. thingy ;)15:19
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CarlFKAUDIO_CAPS="audio/x-raw, rate=48000, channels=2, format=S16LE, layout=interleaved"17:28
CarlFKaudio ... interleaved ?17:29
CarlFKMaZderMind: you mind checking the changes  to I just pushed - I copied the params from and fumbled a bit with getting python string stuff to play nice.18:40
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MaZderMindinterleaved should be sth like joint stereo21:47
MaZderMindi'll check tomorrow, that vhdl stuff is currently more interesting21:48
CarlFKah, right.  as long as it might be valid, that's good enough22:08
CarlFKdid you see my comment about implementing the 1024 / 1280 switch?22:08
CarlFKeven just flipping the current build back to 720p would be nice22:09
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