Tuesday, 2015-02-17

*** tpb has joined #timvideos00:00
*** hait has quit IRC00:27
*** Niharika_ has joined #timvideos02:45
mithroI'm still alive!03:27
mithroshenki: ping?03:30
mithroMaZderMind: ping?03:30
mithrotechman83: are you going to have time to be a mentor again this year?03:34
shenkimithro: hello03:40
mithroshenki: how are things?03:41
shenkimithro: not too bad. how are you?03:42
mithroI get to eat puree food now03:42
techman83mithro, should do03:43
techman83mithro, not moving office again :P03:43
mithrotechman83: aren't you unemployed?03:44
techman83mithro, Nah. I'm still employed.03:45
techman83mithro, though I could be technically could be moving myself to a new office at some point :P - but that should be considerably less effort03:47
techman83xfxf might be though, pending if he found something yet03:50
shenkimithro: \o/04:08
shenkimithro: are you back at work?04:08
mithroshenki: nah, decided to take the week off04:08
mithrotechman83: do you have those photos from the hackfest04:08
techman83mithro: I have to upload them somewhere. I didn't get a lot. But there are a couple of good shots.04:09
mithrotechman83: can you do that ASAP04:09
techman83Let me do that now, then I can mark that off my todo list04:09
*** CarlFK has joined #timvideos04:12
*** ChanServ sets mode: +v CarlFK04:12
techman83mithro: https://plus.google.com/photos/106636702849949888554/albums/611666096154651694504:13
techman83mithro, sorry I didn't get more04:13
mithrotechman83: if you want to procrastiant from doing real work, I could use some help actually writing a blog post to go with the photos04:14
*** sharebrained has left #timvideos04:14
techman83mithro, I've a bit of a backlog of day to day stuff - but if you start a doc somewhere with some paragraph headings I can probably contribute04:15
techman83oh that's right, G+ killed my shortname because it wasn't my real name04:17
techman83(was noting why it was numbers)04:17
techman83I recall being rather annoyed at some point :P04:17
mithrosounds like google plus04:27
*** revsi has joined #timvideos04:30
mithroshenki: any luck with looking at the edid stuff?04:33
shenkimithro: not yet. perhaps tomorrow night i;ll have some time04:33
apsshenki: busy with the WC? :P04:48
shenkiaps: it's been great!05:16
shenkiaps: i went to the india v pakistan game05:16
shenkiaps: i thought i'd been teleported to india. the entire ground was full of indian people!05:16
*** tija has joined #timvideos05:27
mithroshenki: I saw something about 5x more people from India / Pakistan visit for the WC than for the total of the rest of the year05:28
mithrohey tija05:28
tijahi mithro!05:29
shenkimithro: yeah, the place was overrun. they kept the airport open overnight so people had somewhere to stay, as all the hotels were full05:42
tijamithro: A friend of mine wanted to know the image processing project part of speaker track is done or not?05:44
mithrotija: kinda05:44
tijawhat parts  are left?05:44
mithrotija: the big part is getting the PTZ controller stuff into gstreamer06:00
mithroand getting everything working again06:03
mithrotechman83: take a look at that doc again?06:07
techman83mithro, looking now06:08
shenkitija: so what needs to be done to port hdmi2usb to the zybo?06:09
tijaThe architecture of spartan6 and zynq is different. The DDR in sparatan is connected to fpga (ofcourse) but in zynq is connected to PS.06:10
tijaSo we need a VDMA to send data from PL to PS. Also As zynq is a system on chip, major blocks of firmware need a AXI interface.06:11
tijaAlso a vga module is required as zybo doesn't have two hdmi ports06:16
*** sirnam has joined #timvideos06:23
tpbTitle: Ramtin Amin Web Blog (at ramtin-amin.fr)07:10
mithrotija: for a zybo port, you probably only need to worry about getting the HDMI data onto an AXI bus which the ARM chip can then read07:11
tijamithro: do you want compression in PS?07:12
mithrotija: I'd ignore that for now07:12
tijamithro: What you are saying is right. As the HDMI produces data continuously, we need a axi stream interface, then we need a axi VDMA which transfers data form PS to PL.07:16
tijaBut then we need to bring back data into PL for compression, so we need another dma07:17
mithrotija: it would be worth seeing if the ARM core can do compress07:17
tijamithro: I checked that. I think it is difficult.07:20
tpbTitle: Real-time MPEG-2 encoding with ffmpeg (at smorgasbork.com)07:20
tpbTitle: High bitrate real-time MPEG-2 encoding with ffmpeg (at smorgasbork.com)07:21
mithrotija: we have a 1Gigabit ethernet interface to get the data out, so we don't need much compression07:22
mithrotija: does the ARM hard core have any hard accelerators in it too? (Say in the GPU?)07:23
tijamithro: In case we are using ethernet then we don't need to compress for 720p. Atleast this is what Tariq proposed.07:24
mithrotija: possibly07:24
mithrothe Zybo doesn't have SATA right?07:24
tijano it doesn't07:25
mithrotija: I'd work on trying to get a screenshot out of the HDMI input first07:25
mithrothe SERDES in the Zybo are slightly different to the Spartan 6 SERDES07:27
tijamithro: That is easy if you don't want all open source stuff. http://xillybus.com/07:27
tpbTitle: An FPGA IP core for easy DMA over PCIe with Windows and Linux | xillybus.com (at xillybus.com)07:27
mithrotija: you just said "That easy if we don't do what we want to do"07:27
tijaThey give us a fifo like interface and on arm side their driver allows reading from a file just like a tty* thing.07:29
mithrotija: we want the FPGA core to be FOSS07:29
tijaTheir drivers are open source. It would be great if someone can reverse engineer the driver to create a FOSS ip core for the drivers.07:30
tijaThis would ease the use of zynq chips.07:30
mithroit would be nice if the interface on the ARM side was just a V4L device07:31
tijaV4L supports only USB?07:32
mithrov4l is a kernel to userspace interface07:33
*** revsi has left #timvideos07:33
tijaAnyways I can get HDMI screenshot with some hardwork but I will have to use free IPs of Xilinx.07:35
tijaCreating a VDMA core that works is really tough.07:36
mithrotake a look at the misoc / migen stuff from #m-labs07:38
*** Niharika_ has quit IRC07:40
*** Niharika_ has joined #timvideos07:51
*** Niharika_ has quit IRC09:40
*** sirnam has quit IRC11:10
*** sirnam has joined #timvideos11:22
shenkitija: i watched this presentation the other day, about making fpgas easier to use12:13
shenkitija: you might find the ideas interesting12:13
shenkitija: https://www.youtube.com/watch?v=8-OR0QppWKA12:13
tpbTitle: Towards General Purpose Reconfigurable Computing on Novena - FPGAs for Everybody with Novena [31c3] - YouTube (at www.youtube.com)12:13
MaZderMindmithro: pong… somehow12:17
MaZderMindI'm still working on getting the new integration tests pass every time. currently they fail with a 2% probability false-positive12:31
MaZderMindI have an idea what's up but only some minutes a day to work on12:32
MaZderMindin KW11 we have an open yource geo conference we'll be recording, more gst-switch experiments there :)12:32
mithroMaZderMind: okay - I'm around again now12:36
tijashenki: I posted the same link on irc two days ago. :D12:37
mithrotija: it would be nice if the work you did for the Zybo meant that shenki could do his HDMI2Novena module too12:37
mithrotija: I don't think we'd do a gst-switch + speaker tracking in this years GSoC12:41
mithrotija: we want to concentrate on making gst-switch awesome and super stable for the switching case12:42
mithroMaZderMind: have you got a push of your new integration tests somewere?12:42
mithroMaZderMind: I'll take a look and see if I can track down stuff tomorrow12:42
tijamithro: I am don't know the novena architecture well but since it has a spartan6 lx45 with a DDR2 attached to it, porting will be easier. Instead of spitting data out of USB we have to bring it into novena processor.12:45
tijaIn zybo it is a bit differenct because of DDR attached to PS not PL.12:46
mithrotija: the interface between the Novena is an AXI like from what I understand12:46
mithrotija: which is similar how the PS and PL talk in the Zybo12:46
tijamithro: In that case porting to zybo should help.12:47
mithroI think shenki knows more12:48
mithroshenki: I forgot to send some of the adapters back with my parents12:48
MaZderMindmithro: it's a branch in my repo12:49
MaZderMindjust found the pretty old pexpect modukle which does essetially what I'm doing too but is probably better tested and already past the thrweading/blocking issues my code has ^^12:49
MaZderMindI wanted to give it a try today12:50
*** Nooob has joined #timvideos12:50
mithroI should probably go to bed soonish12:51
mithroMaZderMind: still need to finish the moving files around12:51
mithros/still/I still/12:51
MaZderMindhave to do urgent paid work anyway now ;)12:51
MaZderMindmithro: yes, that would probably a good thing to finish first12:52
MaZderMindwhile I'm still playing with the int-tests.12:52
MaZderMindI can't really give promises atm. but if my pexpect-plans work out I might have the rewritten int-tests ready around upcoming sunday12:53
*** f15h has joined #timvideos12:59
*** f15h has quit IRC13:03
*** Niharika has joined #timvideos13:14
cfeltonmithro/shenki/tija: why the port to the zybo? (curious not questioning if)'14:03
cfeltonto utilize the PS?14:05
tijacfelton: Zybo14:52
tijacfelton: Zybo's PS can run a full fleged linux system. As linux has a well developed TCP/IP stack, we can make use of that. Also, porting to zybo will help us port our firmware to Novena which has a similar FPGA/Processor architecture.14:53
cfeltontija: understand, so the answer is to use the PS.14:55
tijacfelton: Ha! yes to use PS14:55
cfeltontija: from the above conversation it is speculative that the port will help Novena, true?14:55
*** sirnam has quit IRC14:57
tijacfelton: I am not well aware of novena architecture. I feel it will be easier to port to novena as it has a spartan 6. All we have to do is send data via axi stream interface to processor and write drivers to capture the incoming data.14:59
cfeltontija: fun stuff, why the Zybo vs. parallela, Zed, etc.14:59
tijacfelton: Zybo is the cheapest of all.14:59
tijaparallela does not have an input hdmi/vga15:00
tijazed is pretty expensive.15:00
cfeltontija: ahh yes, thanks15:01
*** udara28 has joined #timvideos15:01
udara28Hi! I'm udara a student from Univerisyt of Moratuwa, Sri Lanka15:05
MaZderMindThe Zybo is in a Price-Range (~170€) which I would pay to just try out working with your stuff, while the Atlys is a little off (~440€)15:05
udara28is timvideos applying as a mentor organization for GSOC 2015?15:06
CarlFKudara28: yes15:07
udara28CarlFK: thanks :) and looking foward for applying15:08
cfeltonMaZderMind: definitely, yeah the Atlys is a spendy board.15:17
cfeltonanyone have a Zybo yet?15:18
cfeltonMaZderMind/tija: when ordering a Zybo do you need to get the Vivado voucher?15:18
cfeltonmoving to Vivado won't be so fun - ugh15:19
tijacfelton: mithro "loaned" me and rohit a zybo. It did not have a Vivado voucher. They give a 1 month trial which I extend every month.15:19
tijacfelton: Yes moving to vivado is pain. but the block design feature and HLS is awesome.15:20
MaZderMindHum I have not done anything with fpgas yet. is this vivado a requirement? a voucher would be +20€ only, though15:22
cfeltontija: I don't think the Vivado HLS is that great, I have written about it a couple times.  Haven't seen the block design, typically these only seem useful for "toy" examples.  Once you have a large complex system that you want to have many "personalities" the block design sofware fall apart quick (my POV).  Take that with a grain of salt, I haven't used the15:24
cfeltonVivado block thingy15:24
cfeltonYes, Vivado is required for Zynq devices15:24
cfeltonThe voucher seems worth it to avoid the pain of constantly renewing15:24
cfeltonhopefully the voucher isn't tied to a specific Vivado version (?)15:25
tijacfelton: A company working on FPGA where I interned used HLS to port an open source TCP/IP stack to FPGA. The advantage with HLS is that long verification time is avoided. Ofcourse it is still not possible achieve performance of hand written verilog or vhdl.15:27
cfeltontija: why is the verification avoided?15:29
tijacfelton: HLS are bit accurate (atleast the companies claim it to be), so you can write a C code and it's test bench in C and it is good enough to verify you created block. No system verilog is required.15:31
cfeltontija: my take, is that you still need to think in a highly-parallel structure.  Typically this means a different implementation.  Once you work through the appropriate design the imperative C with pragmas buys little (from my experience watching designers trying to use it).15:31
cfeltontija: many do not do verification in V*  Doing verification in C is a negative from my point of view :)15:32
cfeltonI do agree, no SV for verification is a good thing15:33
tijacfelton: Yes that is true. I can't take a normal C code and get good performance on FPGA using HLS.15:33
cfeltontija: my take, is once you structure the approach correctly (what is the best design for the task) the benefits of a C base HLS shrink quickly.15:34
cfeltontija: no disclaimers, my take from my experiences.15:35
tijacfelton: There is other side to it. If you need a core which changes a lot, using rtl is expensive. A small change will require to long cycle of design and verification. Not true if HLS is being used.15:37
*** sirnam has joined #timvideos16:09
cfeltontija: I am not sure if I buy that.  It might be true depending on the design groups experience etc.16:20
cfeltontija: I am sure there are uses but I haven't come across any good examples yet :)16:21
cfeltontija: if you have an example, I would be very interested.  Typically I haven't found much benefit http://www.fpgarelated.com/showarticle/578.php16:23
tpbTitle: Little to no benefit from C based HLS (at www.fpgarelated.com)16:23
tijaHonestly I don't have an example as my industry experience is negligible. What I am saying is out of my experience as intern. I am biased towards HLS because it is my research topic at university.16:35
cfeltontija: it has been a hot research topic for many-many moons.  I am not trying to discourage, I think it is one of those things that looks more promising than it is and there is a plethora of anecdotal examples that keep our hopes alive :)16:50
cfeltontija: I looked quickly at the novena FPGA to CPU interface and it isn't an AXI-Stream (as far as I understand AXI-stream).  It is a memory-mapped interface (data and address) and I would guess with DMA like transfers for bulk data.  I didn't see any throughput numbers though.16:59
tijacfelton: link?17:03
cfeltontija: it is referred to as EIM interface17:03
cfeltonfrom the IRC channel and github https://github.com/bunnie/novena-gpbb-fpga/blob/master/novena-gpbb.srcs/sources_1/imports/imports/novena_fpga.v17:03
tpbTitle: novena-gpbb-fpga/novena_fpga.v at master · bunnie/novena-gpbb-fpga · GitHub (at github.com)17:03
tijacfelton: Novena has a EIM register interface which as you said is a memory mapped interface. And the drivers for the same are already present. So now the bottle neck is sending in HDMI input to fpga.17:21
tpbTitle: novena-fpga-drivers/eim.c at master · bunnie/novena-fpga-drivers · GitHub (at github.com)17:21
tija"Spartan-6 CSG324-packaged FPGA (PVT uses LX45: 43k logic cells, 6.8k slices, 54.5k ff, 401kb distributed RAM, 58 DSP48A, 2088kb block RAM) — has several interfaces to the CPU, including a 2Gbit/s (peak) RAM-like bus — for your bitcoin mining needs. Or whatever else you might want to toss in an FPGA."17:22
tpbTitle: Novena Main Page - Studio Kousagi Wiki (at www.kosagi.com)17:23
cfeltontija: I didn't understand your bottleneck comment?17:28
tijacfelton: We have to create an expansion board so that we can send HDMI signal to FPGA. Otherwise it is easy to port our firmware to novena.17:30
cfeltontija: ic, the expansion interface is slower than the EIM?17:31
tijacfelton: I am not sure. How does that matter?17:32
cfeltontija: I don't think it does, I was trying to relate it back to your comment and understand the context.  Maybe you meant bottleneck as in development and not device performance17:39
tijacfelton: yes development!17:40
*** udara28 has left #timvideos17:51
*** slomo has quit IRC18:31
*** CarlFK has quit IRC18:40
*** Nooob has quit IRC19:24
*** CarlFK has joined #timvideos19:31
*** ChanServ sets mode: +v CarlFK19:31
*** sirnam has quit IRC19:34
*** Niharika has quit IRC19:51
*** tija has quit IRC20:14
*** CarlFK has quit IRC21:35
*** CarlFK has joined #timvideos21:37
*** ChanServ sets mode: +v CarlFK21:37
mithrotija: we have a year licence for vivado21:41
*** CarlFK has quit IRC23:06
mithroThe Atlys board has been discontinued :(23:15
mithroGuess I better hurry up with the prod board23:15

Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!