Thursday, 2015-02-12

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abhinav95Can I get some details about project HDMI2USB#15 ? PDF uploaded on the link "" is not getting opened up and reporting "resource not found".08:13
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tijathis works for me13:49
abhinav95tija: Thanks.14:04
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CarlFK  -  I can't figure out how to flip VGA1 to  mode 5 1024x768 (which works fine with xrandr)17:07
tpbTitle: python-xrandr/ at master · meehow/python-xrandr · GitHub (at
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_florent_Hi guys18:15
_florent_I discovered your project 1 year ago and discussed with mithro some days ago by mail about it.18:15
_florent_HDMI2USB seems really cool! and compressing video is one topic I'd like to work on,18:16
_florent_I'm working at a lower level for now on litescope, liteeth and others stuff using Migen/MiSoC...18:16
CarlFK_florent_: have you done fpga things?18:16
_florent_Mithro seems interested in sharing stuff between HDMI2USB and Migen/MiSoC so if some of you want to18:16
_florent_reuse stuff we developed with M-Labs, feel free to ask or discuss with me :)18:17
_florent_Hi CarlFK18:17
_florent_yes I'm a FPGA designer18:17
CarlFKcool - right now we are kinda stuck on getting the video in18:17
CarlFKgetting the video in reliably18:17
_florent_what are the issues you have?18:18
CarlFKwe get it in most of the time, but too often the device does not show up, and then we have no idea whats going on18:18
_florent_isn't it related to EDID?18:19
CarlFKthey (not me, im just a user) suspect the edid isn't being done18:19
CarlFKthat's the theory, but don't need better debugging tools to better understand it18:19
CarlFKer, don't have... need better18:20
_florent_maybe you can try litescope :)18:20
_florent_I know the m-labs that that worked on HDMI also had issue with EDID18:20
CarlFKoddly enough about 5 min ago I put my board on a shelf thinking "I wonder when I will have something to try" ;)18:21
CarlFKbut im prolly not the person to be trying litescope18:22
_florent_what FPGA are you using on HDMI2USB?18:22
CarlFKim just a cranky user ;)18:22
cfeltondigilent Atlys board is one of the platforms18:23
_florent_about the input video issue, here an HDMI input core developed by sb0 on m-labs:18:24
tpbTitle: mixxeo-soc/mixxeolib/dvisampler at master · m-labs/mixxeo-soc · GitHub (at
_florent_it can maybe be interesting to had a look at what he did for EDID18:24
_florent_it seems to be working reliably18:24
CarlFK  "For developing features for the HDMI2USB system we use a Digilent ATLYS prototype board."18:26
tpbTitle: Planet - Developers News (at
CarlFKXilinx Spartan 6 LX45 FPGA18:26
_florent_OK thanks, that's the same FPGA we are using on Mixxeo (the link I sent)18:27
_florent_about the JPEG encoder, you are using one from Opencores or have you developed your own?18:29
CarlFKdoes that mean you can try these things you recommended i try?18:30
cfelton_florent_: it is the VHDL encoder from opencores18:30
CarlFKnot sure - my guess is Opencores18:30
_florent_Hi cfelton18:30
CarlFKyay - 2 people that can talk intelligently  and I'll just listen now :)18:31
cfeltontest and comparison (in complete of course) of the different jpegenc for opencores18:31
tpbTitle: cfelton/test_jpeg · GitHub (at
tpbTitle: JPEG Encoder :: Overview :: OpenCores (at
_florent_nice thanks, I will have a closer look at that!18:33
cfeltonbest I can tell, the VHDL version (mkjpeg) throughput is much less than the verilog version (,jpegencode different designs) but the verilog version is incomplete, it needs line buffer etc.18:35
tpbTitle: JPEG Encoder Verilog :: Overview :: OpenCores (at
_florent_I'd like to try a JPEG encoder on Mixxeo and do HDMI --> Ethernet (UDP) with LiteEth18:36
cfeltonI recently converted majority of code to verilog (including mkjpeg) so they could use FOSS simulators if they want18:36
cfeltonWe had a GSoC last year that attempted HDMI --> Ethernet18:37
_florent_yes mithro send me some documentation on that18:37
_florent_nice for the verilog convertion, it must take some time...18:38
cfeltonsome but i have a process down so it goes fast, unless I make a stupid mistake it can take some time to debug and find - the process is fairly error prone, not something I would want to do often18:40
tpbTitle: I don’t often convert VHDL to Verilog but when I do ... (at
_florent_thanks for the link :)18:41
_florent_I see you are a MyHDL user, that should help a lot for your testbenchs :)18:46
_florent_(even if I'm a Migen user...)18:47
cfeltonI know18:48
cfeltonodd days ahead18:49
_florent_I have to go, thanks CarlFK and cfelton for the discussion, see you18:53
CarlFKsee ya18:53
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