Thursday, 2014-10-16

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shenkicfelton: that's an interesting point about converting to verilog10:16
shenkithere's no hard requirement; it appears that the Vivado issue can be worked around. my VHDL is rusty enough that I don't know if their proposed solution would make us incompatable with ise10:17
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cfeltonshenki: it looks like the work around would work, if there are no objects I am going to take a swag at converting it all to Verilog.13:32
cfeltonfor the reasons stated above, not that I necessarily prefer Verilog over VHLD but having a single lang source and the FOSS support seems reason enough13:32
tpbTitle: cfelton/gizflo ยท GitHub (at
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