Wednesday, 2014-09-10

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micolousaps: I submitted it in a branch, and you have to manually select the template01:21
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cfeltonmithro: ping03:42
mithrocfelton: pong03:43
mithroI need to add a ~time operation to tpb03:43
cfeltonhola how is your wednesday(?)03:43
mithronot too bad03:44
mithroFinally landed a patch today which was ~3 weeks worth of work03:44
cfeltonalso nice to complete a task03:45
cfelton"always" I meant03:45
mithroso, I wanted to chat about stuff we were chatting about in email, I figured IRC would have a quicker round trip time03:46
cfeltonsounds good, let me grab a stiff drink and we can start :)03:47
cfeltonis there a particular topic, or the whole shebang03:48
mithrowhole shebang I guess03:48
mithrocfelton: I particularly wanted to chat about your hyperion project and how to make MyHDL "take off"03:49
cfeltonme too!03:52
mithroI'd also like to talk a bit more about where I see the HDMI2USB stuff going and where I'd like to be this time next year03:52
mithrowhere did you want to start?03:55
cfeltoneither or, maybe best to see what you are thinking on the direction of HDMI2USB03:55
cfeltonthat would drive what hyperion may or may not be03:55
cfeltonit would be awhile (my guess) for hyperion to catch up to HDMI2USB03:56
mithrocfelton: so, buy the end of next year, I'd like to see the HDMI2USB project have strong support for the following;03:56
mithro  * Multiple "board" support. IE Atlys, HDMI2USB Prod, Zybo, Mixeeo, possibly something from Altera etc03:57
mithro * Multiple "interface" support. IE USB via the FX2, USB3.0/USB2.0 via the Dashio core, Ethernet, AXI (for Zynq + Novena)03:58
mithro * Some type of start for fully open DisplayPort core03:58
mithro * Actively working on reducing all non-100% FOSS parts03:59
mithro * Strong CI testing, IE compile, tests, load onto real device, run on every commit03:59
mithroThe project will kind of be mis named then - but we can figure that out later :P03:59
cfeltonyes, names are just names04:00
cfeltonthey are all great things04:00
cfeltonno major road blocks (i don't think) other than the normal, time, etc.04:01
mithroThe major roadblocks are around project organisation and structure04:01
mithroIE Handling the complexity of the increasing number of "options" and "configurations"04:02
cfeltonyeah, agreed, complexity / scalability grows quickly04:03
mithrothere are also fundamental problems which HDL hasn04:03
cfeltonyes, in the current HDL flow it will be quite a bit of work04:03
mithrothere are also fundamental problems which HDL hasn't really been dealt with yet - IE There should be some type of common shared debug bus.04:04
mithroin some way kinda of like "debug symbols" found in C/C++ shared libraries04:05
cfeltonfpga debugging can be fun :)04:06
mithrocfelton: yes, it's *way* to hard04:06
mithrocfelton: you should be able to quickly query if (and how many times) a fifo has underflowed / overflowed for example04:07
mithroalso, it would be nice to have a FOSS chipscope like thing as well04:08
cfeltonmithro: yeah, having a basic control / status bus is straightforward, that is something that can be built in04:08
mithrocfelton: I didn't say it was necessarily hard :P - although I want it to be reasonable generic so modules can just say "DebugCounter(signal)" and then a magical debug counter gets all set up04:09
cfeltonmithro: the first FX2 interface I wrote used 2 pipe, a streaming and a control/status that drove a WB bus.  Send little read/write packets for standard membus r/w, can add all kind of control and status.04:09
mithrocfelton: I think I saw that when I went searching for MyHDL cores04:09
mithrocfelton: this is -> ?04:10
tpbTitle: USB FPGA Project (at
cfeltonexcept that site will probably die soon, I haven't touched it in years, the host code is on sourceforge and I redid the core part in myhdl and is in the mn repo04:11
mithroI was trying to get Ajit to design something like that - but it didn't really happen04:12
cfeltonI could probably proto something up fairly quick, it is nice on the host to pop up a python interrepter and >> readmem(addr)04:13
cfeltoneasy way to get all those counters :)04:13
mithrocfelton: yeah04:14
mithro <-- that is how I think the HDMI2USB firmware should end up looking04:14
tpbTitle: HDMI2USB Firmware Layout - Google Docs (at
mithro <-- that document talks about Debug interfaces04:15
tpbTitle: Debug Design - Google Docs (at
cfeltonmithro: what do you mean by AXI, AXI is typically an on-chip interface (streaming vs. memmap)04:15
mithrocfelton: The Zynq chips have a Series 7 Atrix FPGA connected to a dual core ARM processor "via AXI" (if I understand correctly)04:16
mithrocfelton: the Novena laptop also uses an "AXI interface" to connect the Spartan 6 core to the ARM chip in it04:16
mithrocfelton: I don't really know much about AXI :P04:16
mithrocfelton: I understood it was just kind of like a memory mapped bus definition or something similar04:17
cfeltonmithro: yes, for a local processor that would be the connection04:17
mithrocfelton: so the ARM chips in those systems are most certainly running Linux, so we have to write a driver which talks to the HDMI2USB firmware via the AXI thingy (and define the interface on the HDMI2USB side)04:19
cfeltonmithro: part of the ARM AMBA spec, AMB is the good ol memory-map and AXI is more of a streaming, higher bandwidth connection.04:19
cfeltonmithro: yes, that could be some work, the vendors will have examples but will have them all wrapped up in there tools04:20
mithrocfelton: there seems to be quite a few hardcore hackers working on the Zynq chips04:20
mithrocfelton: so I'm not to worry about it04:20
cfeltonmithro: cool04:21
mithro <-- another possibly HDMI2USB target04:22
tpbTitle: Parallella | Supercomputing for Everyone (at
cfeltonmithro: have one04:22
mithrocfelton: ah cool04:22
mithrocfelton: so, one thing I wanted to mention is that maybe you could concentrate on making MyHDL the easiest way to "bring up new FPGA dev boards"04:23
mithrocfelton: I mean, I'd prefer you to work on HDMI2USB stuff but it something I wanted to suggested :P04:24
cfeltonmithro: what do you actually mean by bring-up?04:24
cfeltonbasic board exercise, generic test, you mentioned memory tests in the emails04:24
mithrocfelton: say, I just got this dev board (weather because I brought it, or because I just created a new one)04:25
mithrocfelton: the process of getting to the stage where you can do something "useful"04:25
mithrocfelton: start with trying to get a debug interface up04:26
mithrocfelton: once you get that up, start poking at peripherals04:27
mithrocfelton: guess it could also be called "bootstrapping"04:27
mithrocfelton: the advantage by being *the* tool to use to get started with a board, you'll end up with a huge range of boards being supported04:28
mithrosome student will follow the procedure to get random dev board X working and send a patch04:28
cfeltonmithro: sounds fair and a good thing to start working on.04:29
mithrocfelton: it also pretty simple in terms of "cores" until you get to the bigger peripherals04:29
mithroI would expect the process would be something like "get LED to flash", "get LED to flash at a known rate", "get some type of UART working", "get some type of processor/debug bus/chipscope like thing connected to UART", "get USB interface working for faster UART"04:31
mithroI think in a lot of boards, the issue after that is getting offboard RAM working04:32
cfeltonmithro: the first one is already complete for a bunch of boards,
tpbTitle: cfelton / myhdl_tools / source / examples Bitbucket (at
cfeltonmithro: adding USB on the FPGA wouldn't be too hard, pulling together the correct FW and SW takes some coordination04:32
mithrocfelton: 6 boards is a pretty good start - but I can probably list about 100 :P04:33
mithrocfelton: oh, a couple of things I also wanted to mention regarding building communities04:34
cfeltonmithro:  the offboard RAM and reasonable rates shouldn't be too difficult, but I don't want to set expectations incorrect here.  It shoudn't be too bad but I don't know how much time I have each week04:34
cfeltonmithro: adding a  new board is simple, just fill in a little info and viola04:34
mithrocfelton: github is where the coders are - bitbucket might be better in every way but the network effect github is winning04:34
cfeltonmithro: I have repos on both sides, and it appears to not matter one bit which one it is on but rather how much external "marketing" is done04:35
mithrocfelton: I find myself searching directly on github and know other people who do too04:36
cfeltonmithro: yeah but there is so much, you get lost in the noise04:36
mithrocfelton: true04:36
mithrocfelton: btw looking at
tpbTitle: cfelton / myhdl_tools / source / myhdl_tools / boards / xilinx / Bitbucket (at
mithropone.add_port('rx', Signal(False), 88, iostandard='LVCMOS33')04:37
mithropone.add_port('tx', Signal(False), 90, iostandard='LVCMOS33', drive='4', slew='SLOW')04:37
cfeltonmithro: I don't have a strong opinion, new projects I can start where ever, and I can mirror existing project on github, and if the github side has way more traffic can migrate over, at first I won't move my exisiting projects04:37
mithroWhy is that not add "pone.add_device(UART(rx=Pin(88), tx=Pin(90))" or something similar?04:38
mithrocfelton: or does that happen elsewhere?04:38
cfeltonmithro: no, currently you can only associate signals and pins, adding a device here is odd because it still needs to be hooked up in the design04:39
cfeltonmithro: if you instantiate the block here you would also want to add all the options for that block, which could be a little odd.04:41
mithrocfelton: yeah, I guess where you do the configuration depends on the type of block04:42
cfeltonmithro: I do like the idea, of the higher abstraction, get more done quickly, just having trouble resolving some gaps right now04:42
mithrocfelton: My idea of solution would be something like04:43
cfeltonmithro: or multiple of the same but it is possible, then in the top-level you can simple for dev in pone.get_devices():04:43
tpbTitle: Pastebin: 4anfANcj | IRCCloud (at
mithrobut I haven't really thought it all through :P04:45
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cfeltonmithro: I definitely like the idea of the higher abstraction,04:46
cfeltonmithro: why platform instead of board04:46
mithrocfelton: dunno, maybe a "platform" could be a board plus a bunch of expansion things connected or something04:47
mithroIE An Atlys board with a vmodvga connected to the VHDCI...04:47
cfeltonmithro: one of the things that scares me a little, is that there would be high compling of the automate FPGA flow and the cores, right now you the top-level ports would look a little traditional (but still could be automated) but the building of the system would look more like you outlined.04:48
mithrocfelton: I really think setting up a board should be something like this04:48
cfeltonmithro: compling = coupling04:49
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tpbTitle: Pastebin: DWokuzYv | IRCCloud (at
mithrofor maybe something like "DDR2SDRAM(chip=MT389923_DDR2RAM)"04:52
mithrofor example in the Xilinx MIG generator you select the RAM chip type and it automagically sets up all the timing configurations04:52
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mithroso if someone else has a board with the same RAM chip, we should share parameters04:53
mithrocfelton: I get some of that stuff with migen / misoc04:55
mithrocfelton: but its all a bit adhoc / fluffy04:55
cfeltonmithro: thinking04:55
mithrosee and
tpbTitle: migen/ at master · mithro/migen · GitHub (at
cfeltonmithro: I don't think it quite works but i don't have a good rebuttal at this point04:57
mithrocfelton: yeah - it probably has huge holes04:57
mithrocfelton: but a development board as a bunch of ICs soldered to it04:57
mithrocfelton: and those ICs are connected to pins04:58
cfeltonmithro: example, using the base class "Spartan6" is the least interesting info, need package type (IO count), type of XCS6, etc.  Although it looks clean in the short example, I don't know if it would end up being better than ....04:58
mithrocfelton: but I don't really care about the pins really, what I care about are the ICs the pins are connected too04:58
cfeltonmithro: now I see why you call it platform :P04:58
cfeltonmithro: no you don't care about IC, you care about number of resources04:59
mithroof course it gets a little confusing when you add expansion boards04:59
mithrocfelton: "number of resources"?04:59
cfeltonmithro: is it a XC6SLX15 or a XCSLX25  the that that it is a XC6S is not that useful05:01
mithrocfelton: I'm talking about the non-FPGA ICs05:02
cfeltonmithro:  I understand where you are coming from but I don't like the idea of instantiate blocks when defining the IO - then these two are coupled for life.  Bundling IO makes sense and you can define "platforms" with different bundles05:02
cfeltonmithro: we must of got out of sync somewhere, I had use the base-class example ... ahh ahhh ...05:02
mithrocfelton: yeah - i'm totally not tied to the "class Atlys(Spartan6)" bit05:04
mithrocfelton: I was talking about the idea that nobody cares about pins on FPGA, they care about what the pins are connected to05:05
cfeltonmithro: I don't like the idea of forcing a block for and external interface (ext IC) to a block when defining the pins for a board/platform, I am failing to see the logic.  Flipping it, bundling IO and simpling passing the bundles (probably a horrible word but I have been up for almost 20 hours) to the blocks05:05
cfeltonmithro: yes that we agree05:05
mithrocfelton: except for GPIO and expansion ports, it's pretty hard to reconfigure pins which are connected to a device soldered onto the board :P05:06
cfeltonmithro: sure, but I can use different cores to interface with the IC, example, how many FX2 FPGA cores are there.  I don't want to tie my board definition to specific cores - doesn't make sense to me05:07
mithrocfelton: all the FX2 "cores" fundamentally have the same interface to the FX2 IC though05:08
mithroactually, that is a better name for it05:08
cfeltonmithro: I do agree, you want to capture what the IO are connect to, so having something that captures the information is good.   Maybe we are violently agreeing but I jump ahead and assumed the UART was also the logic version an object that contains info on the interface/IC05:09
mithrothe board / platform could be defining "interfaces"05:09
cfeltonmithro: exactly!05:09
cfeltonmithro: then when you create a system you marry the interfaces and modules through something like you example05:10
mithrocfelton: yeah05:10
mithrocfelton: I guess wishbone is an example of an internal "interface" ?05:10
cfeltonmithro:  I do like  pone.add_interface(UARTIntf(Pin(), Pin()))05:11
mithrocfelton: really, even expansion ports are interfaces in some ways, IE "AtlysCompatibleVHDCI" or "PMOD" or ......05:12
cfeltonmithro: yup, but these are the ones that change, but add_interface would work like the add_port, you can override.  not too bad05:13
mithrocfelton: If would be nice to have expansion "Interfaces" you can override a with real devices05:14
cfeltonmithro:  I need to think about this some more, how I see it there would be three packages: board-n-flow, system, and application.05:16
mithroplatform.get_interface("PMOD1").plug(Pmod8LDInterface) or something05:16
mithrocfelton: but that is just thoughts on how I might do something :P05:19
cfeltonmithro:  yeah, might need the concept of: connectors, banks, and interfaces, connectors, banks, and ports represent physical things while interfaces are logical and you should be able to move then around, assign an interface to a connector, bank, or ports  (verbage under review :)05:19
cfeltonmithro:  I need to head to bed, I have to get up in a couple hours.  This was good stuff.  Lets have a couple more collabs and see where it gets us.05:23
mithrocfelton: okay05:23
mithrocfelton: have a good night05:23
cfeltonmithro: you too05:23
mithroback to hitting my head against C++05:24
cfeltonmithro: STL rock on!05:24
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