Wednesday, 2014-07-09

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mithroCARAM_: ping?00:06
mithroaps-sids: ping?00:06
mithromparuszewski: ping?00:06
mithrotariq786: ping?00:06
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mithroayush3504: how's the PCB going?00:28
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mithrohi rohitksingh, how's the VGA requirements going?01:04
rohitksinghmithro: morning! :) Its 6:35AM here. Will resume it after breakfast!01:05
mithrorohitksingh: no worries01:05
puckmithro:  Cool.01:14
rohitksinghmithro: for EDID support for both VGA Source(PC) and VGA Sink(Monitor), we need 4 extra pins (2 I2C lines for each of them). I think I can free upto 3 pins only (OE, COAST and CLAMP ones)01:22
mithrowhat is the VGA chip we are using again?01:23
rohitksinghokay I see we can free one more pin we don't use PWRDN pin.01:24
mithroLooking at the functional diagram at
tpbTitle: AD9984A datasheet and product info | High Performance 10-Bit Display Interface | Analog/HDMI/DVI Interfaces | Analog Devices (at
mithroThe chip seems to support SDA/SCL interface internally?01:25
rohitksinghYes, we need 2 I2C pins separate for AD9984A01:25
mithrorohitksingh: so the AD9984A doesn't have any EDID interface on it?01:26
rohitksinghmithro: No. Its only for initialization and configuration. No inbuilt EDID support01:27
mithrorohitksingh: okay, I hadn't realised that01:27
rohitksinghmithro: I've got an idea...We can hook both AD9984A and the Sink's I2C Lines to same bus01:27
rohitksinghat sink would be at 0x50 and the AD9984A would be at 0x4C01:28
mithrorohitksingh: there are multiple possibilities like that too....01:28
rohitksinghOr, I could simply not use PWRDWN pin, and pull it to ground permanently01:29
mithrorohitksingh: where's the pin mapping spreadsheet again?01:31
tpbTitle: Atlys Expansion Boards Information (using VHDCI connectors) - Google Tabellen (at
mithrorohitksingh: can you fill out the "description" column?01:33
rohitksinghmithro: yeah.01:34
mithroI also think the EDID lines are 5V verse the 3.3V the FPGA provides?01:35
rohitksinghmithro: This page mentions 5V!
tpbTitle: Extron Electronics - Understanding EDID - Extended Display Identification Data (at
rohitksinghSo, We need separate lines for AD9984A, VGA Source and VGA Sink01:39
rohitksinghmithro: The Power Down feature is accessible through AD9984A's registers also. So we can remove the PWRDWN pin01:43
rohitksinghcoming back in 10 minutes01:44
mithrookay, no hurry01:44
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mithrorohitksingh: SERIAL CONTROL PORT The serial control port is designed for 3.3 V logic; however, it is tolerant of 5 V logic signals. Refer to the 2-Wire Serial Control Port section for more information.01:56
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rohitksingh1mithro: i don't think spartan 6 can tolerate 5V? let me check01:59
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rohitksinghmithro: yeah spartan 6 pins are not 5V tolerant02:04
mithroheading to lunch, be back later02:05
JoelwI think the TMDS141 chip on the Atlys does I2C level conversion. For the unbuffered HDMI connectors, I would be a bit wary about the 5V going straight to the FPGA!02:06
JoelwThey do go via the series 50R resistor though.02:06
rohitksinghJoelw: Thanks for the info! Thats what i was wondering that how is HDMI's I2C handled02:08
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shenkiive just been reviewing tija's pull request, and it got me thinking about the formatting of our hdl03:11
shenkiwhat editors are people using to write their verilog/vhdl?03:11
mithroshenki: yeah, that is something I've been holding off on defining03:17
mithroshenki: but we really should have a consistent code style + programmatic checking of code style03:17
shenkimithro: yeah03:19
shenkimithro: im not proposing to reformat existing code03:19
shenkimithro: but as people write new modules, it would be good to do something03:19
shenkii used to use emacs to format my code03:19
shenkiI'd write it in vim (the one true editor), and then run it through emacs to get the style correct03:20
mithroThe best tool I know for linting Verilog is Verilator. Check the --lint-only option if you don't need the simulation.03:20
mithrofrom a stack overflow post03:20
tpbTitle: Intro - Verilator - Veripool (at
tpbTitle: Covered - Verilog Code Coverage Analyzer (at
mithroNot a lint tool, but a coverage analyzer03:25
shenkimithro: so ive reviewed tija's patch03:31
shenkimithro: i split it up into 4 separate patches03:31
shenkii guess I should have gotten him to do that, but I wanted to get stuck into the the code, and it was the most obvious way to make it happen03:31
shenkiit looks good, aside from not matching the existing style in the files he modified (i fixed that up)03:32
shenkiand there's one line that snuck in that shouldn't be there - i think it's from tija playing with the encoding quality03:32
shenkimithro: we also need to settle on a copyright header03:34
shenkisome of the existing ones are a bit... excessive03:34
tpbTitle: VLSI CAD Group Index of Useful Tools (at
mithroVHDL-NICE93 : a VHDL-93 beautifier. This is source with LINUX & SunOS binaries.03:39
mithroVHDL-NICE : a VHDL-87 beautifier. This is source with LINUX binaries.03:39
shenkiSunOS ftw03:44
shenkihere is my fixed up version of tija's code:
tpbTitle: shenki/HDMI2USB at ajit-debug · GitHub (at
mithroshenki: that is the limit of what I found via Google03:46
shenkimithro: did you discuss much more with tija after i left last night?03:47
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mithro seems to support VHDL as a source language03:48
tpbTitle: Doxygen: Main Page (at
mithroappears to be a version of doxygen which supports verilog03:49
mithro seems to support some "language agnostic" checking03:51
tpbTitle: checkstyle - Checkstyle 5.7 (at
mithrobut it's horrible java03:51
shenkiim not very interested in imposing doxygen on anyone03:51
mithroshenki: have you heard of or used SonarQube?04:00
mithro seems to do a bunch of c style languages04:14
tpbTitle: Artistic Style - Index (at
mithroEmacs VHDL-mode has a beautify-buffer command, which works well and is very configurable. I use this all the time04:15
tpbTitle: Hardware::Vhdl::Tidy - (at
tpbTitle: VHDL indent ('93 syntax) - Revised VHDL indent file : vim online (at
mithroemacs -batch file.v -l vindent.el -kill >& /dev/null &04:20
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shenkiemacs -batch hdl/DEBUG/counter_top.vhd -f vhdl-beautify-buffer -f save-buffer04:30
shenkithat's how i do it for vhdl04:30
shenkimithro: i think a friend uses sonarqube for java04:31
shenkior something similar04:31
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shenkitija: hey07:05
shenkitija_: hey07:05
tija_shenki: Hi!07:08
tija_shenki: It seems that the ddr is reading and writing only useful pixels. So no worries in that area.07:15
shenkitija_: good news07:20
shenkitija_: i took a look at your pull request07:20
shenkitija_: some feedback for you: it's often good to split large commits up into smaller, logical cunks07:20
shenkiit makes it much easier for others to review07:21
shenkito demonstrate, i did it for you :)07:21
tpbTitle: Commits · shenki/HDMI2USB · GitHub (at
shenkitija_: i also tidied up some of the changes to existing files so the changes matched the existing coding style07:22
tija_shenki: okay understood, i created a new branch and dumped all the changes to it together. Next time I will take care.07:23
shenkitija_: that's fine07:23
shenkitija_: as far as the brand new files goes, it would be good to follow some kind of coding style07:23
shenkitija_: what editor do you use?07:23
tija_shenki: the one in ISE.07:23
shenkidoes it format the code for you?07:24
shenkior is it free form?07:24
tija_shenki: I find it easier to debug using it. Yes it formates the code.07:24
tija_shenki: what do you use?07:25
shenkii ran your code through emacs code formatting when i committed it, as i like the way it formats the assignment operators with indents07:25
tpbTitle: Add debug module · 3e1a63b · shenki/HDMI2USB · GitHub (at
shenkiyou can kind of script it without having to open up emacs07:26
shenkiemacs -batch hdl/DEBUG/counter_top.vhd -f vhdl-beautify-buffer -f save-buffer07:26
tija_shenki: oh yeah it looks pretty! Which editor you use while coding?07:28
shenkitija_: i use vim07:28
shenkito be honest, i haven't done much vhdl since finishing uni 4 years ago07:28
shenkibut i write all of my python and c in vim07:29
tija_shenki: for python and C I use vim. I use ISE because as soon as you save files you get error messages on ISE terminal.07:30
shenkithat's handy07:31
shenkia contractor i worked with at my last job used ghdl and vim07:32
shenkiand drove it all with python and make07:32
shenkiso you could code similar to with c: type, save, make07:32
shenkiand get warnings07:32
shenkiand then you only needed to fire up the xilinx or altera tools when synthesising for the device07:32
shenkitija_: would you like to submit a talk on your project to an open source conference?07:33
shenkitija_: linux.conf.au07:34
tija_shenki: On the optimisation work I am doing?07:34
shenkiperhaps make it a bit more general about doing open hardware development for FPGAs07:34
shenkibut use your project as a case study07:35
shenkithe reason i think it will be a good talk is that many people at the conference will have a Novena, the open source laptop07:35
shenkiwhich contains a FPGA07:35
shenkiso lots of programmers will be keen to get their hands dirty with FPGAs, perhaps for the first time07:35
tija_yeah that would be great. Plus there are lot of open source fpga platform coming up like arduinos07:36
tija_have you tried papilio?07:36
tpbTitle: mithro/hdl-pretty · GitHub (at
tija_mithro: that is for formatting vhdl/verilog?07:42
tija_okay yes it is for formating07:43
shenkimithro: nice08:00
shenkitija_: what is papililo? (I guess that means i haven't tried it)08:00
tpbTitle: Papilio FPGA Platform (at
shenkitiny fpga :)08:02
shenkinot cheap08:02
shenkithis is an interesting board:,400,1198&Prod=ZYBO08:04
tpbTitle: Digilent Inc. - Digital Design Engineer's Source (at
shenkiAdding HDMI ports would make that a very beefy HDMI2USB v208:04
shenkias it's got a Cortex A9 @ 650MHz08:05
shenkitwo arm cores08:05
shenkiand DDR308:05
shenkigigabyte ethernet08:05
shenkiit's double the price of the papilio08:07
shenkibut far more than double the functioanlity08:07
tija_papilio is meant for hobbyist and is open source. It is more like arduino.08:08
tija_shenki: Can you point me to the license I am suppose to add here.
tpbTitle: Add UART to design · df90a3b · shenki/HDMI2USB · GitHub (at
JoelwYep! If I were designing a new board, I'd probably try to use a Zynq :)08:13
JoelwThey're fairly expensive and BGA only though.08:13
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mithroshenki: Have you seem Joelw's page of low cost FPGA solutions?08:23
JoelwI haven't added some of the new Digilent ones :( They've released a few recently but apparently didn't announce them anywhere.08:39
shenkimithro: what licence are we using for hdmi2usb?08:54
shenkitija_: did you write all of the code that you added in the patch? or is some copied?08:54
tija_shenki: I did not write the UART fifo. Took it from an old project we did in college.08:59
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shenkidoh, he's gone09:06
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tijashenki: I am back.09:15
aps-sidsmithro: Do we have a version of  for gst-1.009:15
tpb<$r> (at
shenkitija: hrm. the ones from college, do you have permission to open source them?09:24
tijaIt was for a course project, I guess we can use it the way we like.09:25
shenkithe other code is licensed MIT09:27
shenkiso we probably want to do the same for yours09:28
shenkiadd a simple header that has `Copyright 2014 Joel Stanley <[email protected]>` at the top09:29
shenkiexcept with your name and email09:29
mithroaps-sids: no09:43
mithroaps-sids: want to give it a whirl?09:44
aps-sidsmithro: so I cannot port that component right?09:44
mithroaps-sids: micolous and thaytan did the initial code09:44
aps-sidsyeah, I can try09:44
tpbTitle: MicroZed | Zedboard (at
mithroany idea how the Atrix-7 compare to the Spartan-6 FPGAs?09:55
mithroThe Artix-7 family delivers 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family and is based on the unified Virtex-series architecture.10:01
mithroInteresting solution ->
tpbTitle: Terasic - All FPGA Main Boards - Cyclone V - Cyclone V GX Starter Kit (at
shenkimithro: i used one of those10:12
shenkimithro: i evaluated the platform for a work project10:12
mithroshenki: it seems to have inbuilt GTPs which are only available on the LX45T series Spartan-6s?10:12
shenkiok. i wasn't looking at the GTPs10:19
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micolousmy ears are burning10:58
micolousYeah, gst-plugins-dvswitch is the dodgeyest hackup of the udp plugin I could do to make it talk dvswitch ;)10:58
micolousBut it worked which is the scary part.10:58
micolousdvswitch protocol is pretty simple, you send a hello message (it's some 4 byte magic documented in protocol.h if I recall) and it just sends you DV10:59
micolousthen you use the DV demuxer in gstreamer to do the hard work10:59
micolousall you need to do is let gstreamer know when your tcp connection drops10:59
micolousSo yeah, your plugin doesn't even need to know DV, it just needs to tell gstreamer it's getting DV11:00
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