Monday, 2014-06-30

*** tpb has joined #timvideos00:00
aps-sidsmparuszewski: is it possible to set some sort of markers to regenerate only the new posts? I know this is how Jekyll works, but regenerating thousands of posts of a 5 year old blog is not wise.00:02
*** CarlFK has joined #timvideos00:17
*** ChanServ sets mode: +v CarlFK00:17
*** CarlFK has quit IRC00:27
*** rohitksingh1 has joined #timvideos01:03
*** rohitksingh has quit IRC01:04
*** rohitksingh1 has quit IRC01:07
*** CarlFK has joined #timvideos01:33
*** ChanServ sets mode: +v CarlFK01:33
mithromorning people?01:37
mithroayush3504: ping?01:37
mithrotariq786: ping?01:37
ayush3504mithro: good morning01:38
mithroshenki / Joelw: ping?02:28
shenkimithro: yo02:29
mithroshenki: so Rohit needs some help with interfacing the VGA capture chip with the FPGA02:30
shenkimithro: k02:30
shenkiwhat's the issue?02:30
mithroshenki: I believe the clocking in of data and dealing with skew02:31
mithrohe has a lot of info on his blog post02:31
* shenki reads02:31
Joelwmithro: Hi!02:31
mithroJoelw: you could probably help here too02:32
*** tija_ has joined #timvideos02:33
shenkimithro: hrm, which blog post?02:34
JoelwProbably this one?
tpbTitle: vMod-VGA: Current Status and Road Blocks - Google Docs (at
tpbTitle: Planet - Developers News (at
mithro <-- I think that is the first one to start on02:34
tpbTitle: [GSoC Daily Log]: Drivers and PLL | Dreams eXtrinsic (at
shenkiright, i read that02:35
*** tija has joined #timvideos02:35
mithrothe following blog posts talk about things he's tried02:35
shenkiah, the google doc is good. thanks Joelw02:35
mithrohe's capture the summary at the doc Joelw linked02:36
JoelwHmm.. constraints might help? Doesn't look like the timing relationship between R/G/B and the clock is defined? Though oversampling and trying to detect the eye dynamically would get around that.02:40
mithroone big problem is he doesn't have any scope access it seems02:48
JoelwA scope may or may not help! :) You'd probably want a high bandwidth one with a large sample memory so that you can dump an entire line into a file and compare what it sees and what the FPGA thought it got02:52
JoelwThough the 24-bit VGA signals probably aren't that high bandwidth02:53
mithroyeah, I suggested he start with doing a very low resolution like 320x24002:53
JoelwSo yeah! A reasonable scope would be good. He doesn't have access to one at his university?02:53
JoelwWhen I was doing something like that at uni I borrowed a 4-channel 1GHz monster02:54
*** CarlFK has quit IRC03:02
*** CarlFK has joined #timvideos03:03
*** ChanServ sets mode: +v CarlFK03:03
*** loadstar91 has left #timvideos03:23
aps-sidsmithro: I'm unable to find faac-encoder component in timvideos' flumotion repo. Is it from some other repo?03:30
aps-sidsmithro: gst-flv-muxer also03:33
aps-sidsx264-encoder, faac-muxer, lamemp3-muxer  as well03:41
mithroaps-sids: There are multiple flumotion repos referenced from that. Check the submodules.05:16
ayush3504mithro: so, we were discussing about no. of slots to have?05:59
mithroayush3504: so, we have a limit of 6 slots by the number of pins in the VHDCI06:02
ayush3504mithro: yes06:02
mithroayush3504: we also have a bunch of mechanical restrictions if we want to fit it in 1ru racks06:03
tpbTitle: Serial expansion board and daughterboard design - Google Tabellen (at
ayush3504mithro: yeah i have that open06:05
ayush3504mithro: 1 rack unit is 482mm right?06:05
mithrowhat does Wikipedia say?06:06
ayush3504mithro: wikipedia says it's a unit of height for 19", 23" racks06:06
tpbTitle: Rack unit - Wikipedia, the free encyclopedia (at
mithroayush3504: I don't see any reason not to trust wikipedia06:10
ayush3504mithro: so we're considering 19" 482mm racks right?06:11
mithroA front panel or filler panel in a rack is not an exact multiple of 1.75 inches (44.45 mm). To allow space between adjacent rack-mounted components, a panel is 1⁄32 inch (0.031 inch or 0.79 mm) less in height than the full number of rack units would imply. Thus, a 1U front panel would be 1.719 inches (43.66 mm) high. If n is number of rack units, the06:11
mithroformula for panel height is h = (1.750n − 0.031) inch = (44.45n − 0.79) mm.06:11
mithrothat is what wikipedia says, so I think we should follow that?06:12
*** slomo has joined #timvideos06:13
*** slomo has joined #timvideos06:13
ayush3504the height doesn't seem to be related to no. of slots. the daughterboards should fit nicely into that height.06:14
mithrowe also care about the width right06:23
mithroThere are a couple of ways I could see this mounted06:23
mithroa) The board and the Atlys side-by-side in a single case06:24
mithroThe two choices for the "width" of the (a) case is the "A/V half rack" width and the full 19 inch width.06:25
mithrob) The board is mounted in it's own case. The Atlys is mounted in it's own case. A VHDCI cable is run between the two cases.06:25
mithroAgain the widths of the (b) cases should be based on the "A/V half rack" width and the full 19 inch width.06:25
ayush3504mithro: ok, how expensive is a VHDCI cable?06:31
JoelwI think I got one on eBay a few years ago for about $4006:31
ayush3504that looks expensive for running low speed signals06:33
JoelwYeah, and the cables are pretty fat and un-bendable. If you only wanted low speed, you could build a breakout that converts it to a 40 pin IDC header or something06:35
ayush3504yeah, but even that turns out to be >20$ with each connector around 10$. right?06:36
JoelwPretty much, yeah!06:36
ayush3504for option b) i would suggest connecting the box just through the USB on PIC18F we're planning to have included.06:36
JoelwThough if you were going to use low speed, your second board could just be a 40 pin IDC, so you'd only need one VHDCI06:36
ayush3504Joelw: yeah, that's better06:37
JoelwIf it was a one-off, you could just unsolder the VHDCI connector and solder on a ribbon cable! :)06:38
ayush3504on the atlys?06:38
JoelwYep! I probably wouldn't want to butcher mine up like that though.06:38
ayush3504yes, i was going to say that too :P06:39
mithroayush3504: we can probably make our own crappy low speed VHDCI cable06:39
ayush3504mithro: why does it have to go through the HDMI2USB if it's in a separate box?06:40
mithroayush3504: it doesn't *have* to, but it would be good to keep the option open to do so06:40
ayush3504mithro: okay06:40
*** mparuszewski has quit IRC06:42
ayush3504mithro: so i see we can fit 11 (or maybe 12) or 5 daughterboards into a 19" and half rack respectively06:42
ayush3504mithro: ok06:43
mithroassuming the spreadsheets calculations are right06:43
mithroayush3504: which I think you should probably give a good checking06:43
ayush3504mithro:  case width L17 is based on the material thickness right?06:44
mithroayush3504: can't remember, take a look at the formula's06:44
ayush3504mithro: looks correct06:49
mithroayush3504: okay06:56
mithroayush3504: so after looking at all that, what do you think we should set the number of daughterboard slots too?06:57
ayush3504mithro: PIC18USB might be able to support 7 or 8 serial ports. I don't know whether it will be able to handle simultaneous bitbanging of the ports06:58
ayush3504mithro: and VHDCI supports 606:59
mithroayush3504: I'm interested to know how you plan to fit 6, 7 and 8 daughterboards into the space which only fits 507:00
ayush3504mithro: i don't have plans to fit more than 5 dboards into half av rack07:01
mithroayush3504: so after looking at all that, what do you think we should set the number of daughter board slots too?07:02
ayush3504mithro: either we can remove one, or the 6th daughterboard can be placed arbitrary elsewhere in the case, connected with a ribbon cable07:04
ayush3504mithro: for 6th dboard we can have an altered pcb with 5 slot length, and extra header for 6th slot07:04
ayush3504mithro: width*07:04
mithroayush3504: we could just choose to do 5 slots, right?07:05
ayush3504mithro: sure07:05
mithroayush3504: looking at the spreadsheet, the other number of slots is, 2 right?07:06
ayush3504mithro: yeah07:06
mithroayush3504: so, if we go with 5 slots, we get back a bunch of pins on the VHDCI connector right?07:08
ayush3504mithro: yeah that's what I was thinking about. frees up pins for SPI as well07:08
*** slomo has quit IRC07:09
*** slomo has joined #timvideos07:10
mithroayush3504: I think that probably sounds like a good idea then?07:11
ayush3504mithro: sounds good to me as well07:11
mithroayush3504: we should make sure it is possible to trim the same board back to 2 daughter boards too07:12
ayush3504mithro: you mean laying out the board in such a way that we can cut it to 2 slot width, right?07:13
mithroayush3504: yes07:14
ayush3504mithro: okay07:14
ayush3504mithro: would put dotted lines on slik screen for that.07:14
mithroayush3504: did the symlink method of the shared subsheets work?07:17
mithroayush3504: did you end up fixing up the busses?07:17
ayush3504mithro: yes it works07:17
ayush3504mithro: nope didn't try that yet07:18
mithroayush3504: I think getting the motherboard schematic ready should be the top priority now we have a good understanding the the slots and layout07:19
ayush3504mithro: sure07:19
mithroayush3504: we should get the PCB design up too07:22
ayush3504mithro: ok07:23
mithroayush3504: just the general layout, not all the traces and stuff07:23
mithroayush3504: with the daughterboard stuff07:23
mithroayush3504: I'm wondering if the daughterboard should be a "library component" or something?07:23
ayush3504mithro: yes it is already similar to library component, it can be imported as a hiearchical sheet07:24
ayush3504mithro: you can create a pre-customized board by pasting the "standalone" sheets in daughterboard folder to the daughterboard slot page07:28
ayush3504mithro: what to do with free pins on PIC18F, LEDs? ;)07:39
aps-sidsCarlFK: mithro: I need to travel for some university work so I might not have internet availability for next 3 days or so, but I would still be working on the project.09:47
*** rohitksingh has joined #timvideos09:53
mithroayush3504: I was more talking from a PCB point of view11:09
mithroayush3504: got anything for me to review yet?11:10
ayush3504mithro: J port is free on PIC18F. what to do with it?11:10
mithroayush3504: we can worry about that later I think11:11
ayush3504mithro: yes, that's a good idea. daughterboard as a PCB component would help with clearances11:11
mithroalso means you update the component once and it should update all of them11:16
mithroayush3504: got something for me to review before I head home?12:28
ayush3504mithro: check github. bus did not work12:28
mithroayush3504: did not work is not a useful description12:29
mithroplease explain what didn't work12:29
ayush3504mithro: >200 DRC errors all suggesting that pins are not connected12:29
ayush3504mithro: i've commited the changes for yo to see the schematic12:30
mithrookay, will look in a minute12:30
mithroshenki: first run boards are back from production! They look pretty awesome!12:34
rohitksinghmithro: Hi! You mean HMDI2USB production boards? Awesome! :)12:40
*** rohitksingh has quit IRC12:41
mithroayush3504: commit I should be looking at is e0792eb586bea6cecf3692d1285553a785cf0c54 right?12:45
ayush3504mithro: yes12:46
mithroayush3504: btw I did tell you that if you put "Issue #X" in your commit message github will automatically add the commit to the issue?12:47
ayush3504mithro: oh ok, didn't know that12:48
mithroayush3504: I'm sure I mentioned it in one of the git issues12:49
mithroayush3504: If you write "Fixes #XX" github will even close the issue for you12:49
mithroayush3504: okay - why are you still doing one huge bus? I'm sure I told you that you should be doing 1 bus per serial port?12:50
ayush3504mithro: you said "With a single BUS pins need to be named 1->38, doing 1-6 multiple times is just the same set of pins, that is not what we want."12:51
ayush3504mithro: that's why12:51
mithroayush3504: do you see the screenshot I uploaded?12:52
ayush3504mithro: yes, i saw, but you suggested it later so i did  that. The bus should work whether it's 6 busses or a single bus12:53
mithroayush3504: in you are using one huge bus12:53
ayush3504mithro: that's old12:53
mithroayush3504: with you are still using 1 huge bus12:54
ayush3504mithro: this is also old, did you check the latest commit?12:54
mithroayush3504: yes, you have continued to use one big bus rather then the multiple smaller buses I was suggesting multiple times12:55
ayush3504mithro: " "With a single BUS pins need to be named 1->38, doing 1-6 multiple times is just the same set of pins, that is not what we want."" -- but then what does this mean?12:55
mithroayush3504: It's referring to
ayush3504mithro: ok, but technically this should work:
ayush3504mithro: and 30 pins is not huge12:58
tpbTitle: Dropbox - Untitled1.png (at
mithroayush3504: you need to use a wire between the bus and the hierarchy pin I believe...12:59
mithroI'm just testing now12:59
ayush3504mithro: i think the bus needs to be expanded with all its pins as i did in each sheet13:00
*** FeltonChris has quit IRC13:09
mithrookay, I just tested a simple example and it works13:14
*** FeltonChris has joined #timvideos13:16
ayush3504can you suggest a change in my schematic that would make it work, or can you share you example13:16
ayush3504btw, a wire between the bus and hierarchy pin isn't used in the link you had shared:
tpbTitle: Radiation Laboratories: Kicad: How to use a Bus with Hierarchical Labels? (at
mithrogit push -u origin master13:23
tpbTitle: mithro/scratchpad · GitHub (at
mithroayush3504: firstly you want to set your pin types to tri-state13:24
ayush3504mithro: which ones13:25
mithroall the bus ones13:25
mithroBTW 5V / GND / etc shouldn't be type in/out13:25
mithrothey should be type "passive"13:25
ayush3504ok, those were to suggest that the PIC and VHDCI are sources and the middle sheet in a sink13:26
ayush3504but, i'll do that13:26
ayush3504these are not related to bus errors however13:27
ayush3504the errors i get say "not connected"13:28
mithrookay it seems when ever you change a heirch label in the sheet you have to delete the top level label and add import it again13:34
mithrothat fixed the bus problem13:35
mithroI have to run home now13:36
ayush3504mithro: i tried you example. it works.13:36
ayush3504mithro: "add import it again" means?13:36
mithroayush3504: I'll be back in 30 minutes13:36
mithroOn the top level, delete the pin inside the sheet block13:43
mithroClick the import pin tool13:43
mithroAdd the pin back onto the sheet blocl13:43
ayush3504mithro: yeah got it did that just now13:43
ayush3504mithro: reduced errors to 9113:43
ayush3504mithro: putting back the top level labels fixes all13:45
mithroI think you need to do that any time you change the pin13:46
mithroFixing the in/out of the power should fix some more13:47
ayush3504mithro: ok, got it. Just wondering how reliable this feature is, since it's not documented in their documentation it seems?13:47
ayush3504mithro: no, fixed all.13:47
mithroPlease change to one bus per serial port13:47
mithroAnd document the bus pin to serial pin mapping at the top level13:48
ayush3504mithro: are you sure? one big bus is easier to manage. labels get added easily pressing the Ins key13:48
mithroYes. It fits more logically13:48
ayush3504mithro: k13:48
mithroIt is also clearer what happens if you chop off serial ports13:49
mithroYou lose the bus rather then losing random pins 45 to 9813:50
ayush3504mithro: true13:52
mithroPlus the bus doesn't map directly to the vhdci header either13:55
mithroBusses are to logically group related things together13:56
mithroayush3504: I'm just going to have some dinner and then go to bed13:57
mithroayush3504: I'd like to see this schematic finished and a start of a template for the daughtboard PCB13:58
ayush3504mithro: sure, thanks for the help13:58
mithroayush3504: how is the requirements document going?13:59
ayush3504mithro: much more updated than before14:00
mithroayush3504: I think we should just connect port J to some general PMOD headers?14:04
mithroI can't think of anything else useful for it?14:04
ayush3504mithro: ok, so basically it will be a header with pmod pinout14:05
mithrolooking at the layout of the PINs for Port J (around the edge of the PIC) it's kind of got an annoying layout too14:05
mithroayush3504: so we should leave it to last and only do it if we can make it work without screwing up the PCB14:06
tpbTitle: Sign in - Google Accounts (at
ayush3504mithro: yeah, ok14:07
mithroit's not mapped to any useful hardware either14:07
ayush3504mithro: can you tell me about the new page on spreadsheet, i don't understand it14:08
mithroayush3504: you are looking at the PIC chip from above14:11
mithroayush3504: each cell is a pin on the PIC chip14:11
mithrothey are color coded into groups14:11
ayush3504mithro: got it14:11
mithroPORTA is that dark red/brown color14:11
mithrojust a nice way to visualize the pins14:12
mithroyou can see how the purple, PORTJ is kind of split all over the PIC pins in a non-useful manner14:12
ayush3504indeed, that's quite useful14:12
ayush3504mithro: yeah, collecting them at a spot like header would make routing difficult. there will be more vias i guess14:15
mithrowe'll see how we go14:16
mithroayush3504: where did we get with making the daughterboards compatible with PMOD spec?14:18
ayush3504mithro: i did that14:18
ayush3504mithro: i've changed the daughterboard header if you see the daughterboard slot sheet14:18
tpbTitle: Changed daughterboard slots to support Digilent PMOD and changed label n... · 524fed0 · ayushsagar/HDMI2USB-vmodserial · GitHub (at
ayush3504mithro: also updated the drawing14:19
mithrolink to the drawing?14:20
tpbTitle: Support pins and headers on daughterboard - Google Zeichnungen (at
ayush3504mithro: it's all according to the PMOD specs you had sent14:21
ayush3504mithro: the link is there in the drawing14:21
mithroayush3504: what about the pin mapping?14:21
ayush3504it's there in the daughterboard slot sheet in schematics14:22
mithroayush3504: which one is that?14:23
mithroDaughterboard slots.sch ?14:23
ayush3504mithro: yes14:24
tpbTitle: Dropbox - Untitled2.png (at
ayush3504mithro: compare it with page 9,
ayush3504mithro: don't follow the numbering14:25
tpbTitle: PMOD Pins - Google Tabellen (at
mithroayush3504: so regarding the PCB, I was thinking we should look at hackvana14:54
mithroayush3504: and we should target Friday14:55
mithroayush3504: take a read of
tpbTitle: Hackvana PCB Q - Google Docs (at
mithroayush3504: and ask on #hackvana if you have any questions14:55
ayush3504mithro: okay14:55
mithroayush3504: if we are good, we can get the boards in roughly 5ish days14:56
mithroayush3504: which interface are you using for the pmod headers?14:56
ayush3504mithro: gpio i guess14:57
ayush3504mithro: i placed vcc and gnd at right places, rest are connected to gpios14:57
mithroayush3504: here is some stuff from #hackvana14:58
mithro12:39 AM <hackvana> First, take my guide and have your student read it from beginning to end, especially regarding the checking of the design.14:59
mithro12:40 AM <hackvana> Second, ask for review help in here.14:59
mithro12:40 AM <hackvana> Third, send me a preliminary design so I can do things like make sure the zip is basically seaworthy14:59
mithro12:41 AM <hackvana> Fourth, the student should register on, and then send me the nickname they'd like to use in an email.14:59
mithro12:41 AM <hackvana> I suggest you ask for a quote earlier than later14:59
mithro12:41 AM <hackvana> Yes.  If files are missing or not named correctly, or there are format errors, well it's going to take time to correct.14:59
mithro12:42 AM <hackvana> I have handled several tens of thousands of PCBs.  I'm basically wording you up on the most common pitfalls so your student can avoid them.14:59
mithro12:58 AM <hackvana> mithro: Please get your student in here soon.  We'll help them as much as we can.15:00
mithroayush3504: so you should join #hackvana channel15:00
ayush3504mithro: sure, thanks15:02
ayush3504good night15:15
*** slomo_ has joined #timvideos17:48
*** slomo has quit IRC17:51
*** rohitksingh has joined #timvideos18:00
*** mparuszewski has joined #timvideos18:24
rohitksinghany mentors online? shenki, Joelw, CarkFK, FeltonChris, and anyone who could help in hardware? mithro is probably asleep. I'm really sorry for my peculiar timings...Its just more convenient to work at night here18:26
*** rohitksingh1 has joined #timvideos19:03
*** rohitksingh has quit IRC19:03
*** rohitksingh1 is now known as rohitksingh19:03
*** slomo_ has left #timvideos19:43
*** slomo has joined #timvideos20:16
*** rohitksingh has quit IRC22:44

Generated by 2.12.1 by Marius Gedminas - find it at!