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| nimh | @tmichalak thanks, that makes a bit more sense, although I still don't get how to map it to the synthesis parameters you'd have in the verilog instantiation. If I look at the docs for the dsp slice there is a parameter called ACASCREG which can have values of 0,1 or 2 (so I suspect it needs at least two bits to represent) and a separate param called AREG which again can be 0,1 or 2. Not sure how those | 18:38 |
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| nimh | map to that single fasm_param? | 18:38 |
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