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| tristanC | Hello again, so I'm getting `Warning: Couldn't find port matching sw[0]` and `ERROR: set_property IOSTANDARD: Incorrect number of arguments.` when running symbiflow_synth with the xdc file provided by digilent for the nexys a7 board. | 01:19 |
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| tristanC | and it seems like this is a known issue according to https://github.com/gergoerdi/clash-pong/commit/237d811f98de6ce1e480788af4f3b768dc8c3f27 , but i'm not sure what to do for the SW pin... | 01:21 |
| tristanC | well, removing most of the set_property fixed the error and a bit file got generated, but that does not seems right :) | 01:22 |
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| sf-slack | <gergo> Yeah it seems that Vivado is happy with the .xdc file containing unconnected ports, but Symbiflow isn't. So you unfortunately have to make a design-specific version of your .xdc file that removes or comments out all unconnected ports. This sucks because it means you can't share a single canonical .xdc across projects :( | 10:33 |
| sf-slack | <gergo> Xilinx ISE has the same problem btw. Maybe I should add some build-time rules to generate the `.xdc`/`.ucf` files by starting from a template and stripping out unused ports | 10:38 |
| sf-slack | <gergo> I assume due to the nature of this project, people here have some grasp of FPGA-related IP questions? Can someone maybe help me out with https://opensource.stackexchange.com/q/12176/4120? | 10:41 |
| tpb | Title: licensing - Including design reference implementations with open source program - Open Source Stack Exchange (at opensource.stackexchange.com) | 10:41 |
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| tristanC | @gergo hello, I see thanks! | 13:18 |
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