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| sf-slack | <fahrenkrog> Hi all, I'm wondering what verilog/vhdl editors you are using? I've been trying VSCode for Linux, it works ok, highlighting is OK, but I can't get the outline to work. I installed the Verilog-HDL/SystemVerilog extension, but I must have configured it wrong or it's not active for my project. Any other suggestions I'm happy to try out. Cheers, Alberto | 07:52 |
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| lkcl | FOSDEM2022 Call for Papers is now open - we've established a new devroom, Libre/Open VLSI/FPGA Hardware https://libre-soc.org/conferences/fosdem2022/#cfp | 12:10 |
| tpb | Title: fosdem2022 (at libre-soc.org) | 12:10 |
| lkcl | papers welcome on symbiflow, toolchains, tape-outs, workflow, anything and everything related to FPGAs and VLSI | 12:11 |
| lkcl | please do distribute | 12:11 |
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| mithro | @acomodi / @kgugala - Does the symbiflow yosys->vpr flow support DSP? https://twitter.com/BrunoLevy01/status/1465028419872346119 and https://twitter.com/mithro/status/1465148162935382017 | 16:16 |
| sf-slack | <acomodi> @mithro: For VPR we lack the definition of the primitive in the architecture so DSPs are not supported in the yosys->vpr flow | 16:19 |
| mithro | acomodi: Which means that Bruno must be using a different flow, right? | 16:20 |
| sf-slack | <acomodi> Right | 16:20 |
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