Thursday, 2020-06-11

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HackerFooacomodi: With fpga-tool-perf, for `python3 --toolchain nextpnr-xilinx --project blinky --board arty`, I get this:04:17
* HackerFoo sent a long message: < >04:17
HackerFooUsing nextpnr-xilinx 7e46c6a3703d029c9776d57b64e4ba94f7bc826404:18
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hexastormhey all, i am building a laser scanhead with a ice40 fpga... but have some problems configuring the flash memory09:40
hexastormmy schematic is here
tpbTitle: firestarter/pi_hat at master · hstarmans/firestarter · GitHub (at
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hexastormcdone pin of my ice40 fpga is low ... i am able to switch the fpga between slave and master mode...09:41
hexastormbut i am not able to write to the flash memory...09:41
hexastormif i cut the power to the fpga (CDONE pin goes to 1 as it is no longer pulled down by the ice40) ... I am able to congfigure the flash memory09:42
hexastormso ... i have the feeling i am in the situation that the FPGA is working.. but is somehow interfering with me communication with the flash memory and i cannot disable this09:43
Loftyhexastorm: you should ask in ##openfpga I think.09:45
hexastormokay thanks lofty!09:46
daveshahIf you assert (set low) CRESET and keep it low, then the iCE40 should release the flash09:59
hexastormif i pull the CRESET low... it does have an effect.. the FPGA is no longer polling the clock pin...10:03
hexastormi can flip all the SPI lines.. but cannot write to memory.. only receive bytes 255 or slave out seems to remain high10:04
hexastormcould i try programming the FPGA without using the flash memory?10:05
tnthexastorm: did you put a pullup on CDONE ?10:41
tntnm ... I hadn't read the whole backlog.10:43
tntMy guess is you're just not driving the flash correctly ...10:43
hexastormyep have a pull up at cdone...11:17
hexastormalso considered the fact i am not driving flash correctly.. but made a board without fpga... ( it works) and on the current board it also works if I disable the supply voltage at 1V... but something must be wrong :-)...11:23
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tnt"Error 1:"12:04
tntWell that's just the best error message ever.12:04
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hexastormokay well i fixed it12:55
hexastormit is the flash ram chip12:55
hexastormi dont know how this is possible .. but this chip doesnt work well alongside the fpga12:55
hexastormi solderd the flash memory from the icezero to my board and this fixes the issue..12:56
hexastormif i only use the flash memory this also works12:56
tntAfter configuration the ice40 puts the flash to sleep.12:56
tntyou need a wakeup command.12:57
tnt(and some flash chips don't support the sleep command and so they work even if you don't wake them up because they never went to sleep in the first place)12:57
hexastormbut will it work with the ice40.. i will look for the wakeup command12:59
hexastormi am using this chip S25FL064LABMFI010 will look for wakeup13:00
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hexastormokay... the vendor which has working memory is known as micron.. the one without working memory is known as cypress.13:03
hexastormcan't seem to find section with wakeup in the cypress manual13:03
hexastormIn DPD mode the device responds only to the Resume from DPD command (RES ABh).13:05
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sf-slack<timo.callahan> My PR #1515 failed a test that seems to be a network issue -- is there a way to restart the test (other than pushing an empty commit)?   Here's the log:
tpbTitle: WIP -- Initial support for Artix 100t parts by tcal-x · Pull Request #1515 · SymbiFlow/symbiflow-arch-defs · GitHub (at
HackerFootimo.callahan: Set the `kokoro:force-run` label.15:27
HackerFoo(I've done it for you)15:27
sf-slack<timo.callahan> Thanks, got it!15:36
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ryancj14@acomodi I'm getting an error in fpga-tool-perf when I go into the test folder and run where it is unable to import the Timed class from utils. Do you get the same error?16:53
ryancj14File "/home/student/fpga-tool-perf/test/../", line 16, in <module>16:53
ryancj14    from utils import Timed16:53
ryancj14ImportError: cannot import name 'Timed' from 'utils' (/home/student/fpga-tool-perf/conf/src/prjxray/utils/
-_whitenotifier-f- [symbiflow-examples] mithro opened issue #19: Change to environment.yml -
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