Thursday, 2020-01-02

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-_whitenotifier-5- [symbiflow-arch-defs] YFWang97 opened issue #1256: make buttons_basys3_vivado failed due python assertion -
sf-slack<davidetoldo> Hi guys, chiming into the project after a couple years again. How is it going? Are Artix 7 devices working well with SymbiFlow now? Saw the new front page, looks promising :-):v::skin-tone-3:02:33
sf-slack<davidetoldo> I still have my Nexys 4 DDR and am interested in getting back into FPGA again :)02:33
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sf-slack<brock.michael12345> Hi all, similar to above... Though I am just getting started with FPGAs..... I'm wondering how I can help? I see the effort to document the bitstream.... I have a reasonable amount of compute power absolutely to me, would running all the experiments and tests be of help?14:19
Xiretzasf-slack: heh, I came in here asking the same question a while ago, and it turns out the fuzzers are run exhaustively by the CI already. what needs to be done apparently requires actual knowledge and skill (which I don't really have either), things like writing minitests and new fuzzers.14:23
sf-slack<brock.michael12345> Yeah ack...... Both of those I currently lack.... I'll keep poking around to see what I can do to help...14:43
sf-slack<kgugala> Hi @davidetoldo @brock.michael12345 @Xiretza14:44
sf-slack<kgugala> there are quite a few things left in the documentation effort14:44
sf-slack<kgugala> for 7 series those are mainly dedicated blocks like transreceivers, pcie, dsp14:45
sf-slack<kgugala> there is some work left on IOs and IOstandards14:45
sf-slack<kgugala> If you have FPGA skill you can always start from adding a minitests for certain fetures of those14:46
sf-slack<kgugala> also there are some tasks marked as "good first issue" on github14:46
sf-slack<kgugala> I thinks this may be a good start point14:46
sf-slack<kgugala> we're here and can always discuss things in details either on this channel or in GitHub issues14:47
sf-slack<davidetoldo> Okay thanks! I’ll have a look if I can contribute something wrt those minitests. I do know Verilog quite well and have worked with FPGA and Vivado before.14:51
sf-slack<davidetoldo> Is it possible to use SymbiFlow with the 7 series even though it’s not 100% documented? Like, can you use part of the LUTs then?14:52
sf-slack<kgugala> yes, that works14:52
sf-slack<kgugala> we have some problems with IO standards preventing external DDRs from working14:53
sf-slack<kgugala> but LUTs, FFs, BRAMs, DRAMs, SERDESes work fine14:53
sf-slack<kgugala> simple IO's also work14:54
sf-slack<kgugala> so you can implement a CPU using only BRAMs and uise e.g UART/I2C for communication14:54
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sf-slack<kgugala> there is still a lot of work to do14:56
sf-slack<kgugala> but if you want to play around with it and experiment, you already can14:57
sf-slack<brock.michael12345> Thanks for the tip about the issues! Which repos should o be looking at for those? Mainly things that don't require in depth existing knowledge of an fpga... I'm a young Ee and good at picking things up, but this amount other smaller experiments puts my first on depth usage of fpgas14:58
sf-slack<kgugala> so this one is for documenting 7 series14:59
tpbTitle: GitHub - SymbiFlow/prjxray: Documenting the Xilinx 7-series bit-stream format. (at
sf-slack<kgugala> this one is for toolchain14:59
tpbTitle: GitHub - SymbiFlow/symbiflow-arch-defs: FOSS architecture definitions of FPGA hardware useful for doing PnR device generation. (at
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sf-slack<brock.michael12345> Ahh that makes more sense now.... I also had a massive pebcak.... Most of the time I've been looking into this has been from my phone.. But the github app for some reason isn't loading the issues.. But I opened that on Firefox and now they appear... Now I just feel silly...15:02
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Xiretzadaveshah: I know nextpnr-xilinx is highly experimental and all, but I can't get it to compile anything at all, including the two arty examples. it always ends in "failed to find a route".18:24
daveshahXiretza: I just pushed a fix for that, I think18:29
daveshahIt was a result of a Yosys change that created inv cells18:29
Xiretzadaveshah: oh, whoops, sorry about that. always pull before complaining ;) I knew I had gotten farther before, but with so many interconnected parts I didn't think of downgrading yosys.18:34
daveshahWeirdly I had the same thing this morning18:34
Xiretzagreat, now that that works again, is there free tooling for writing bitstreams to Arty boards yet or does that still need Vivado?18:50
daveshahEither xc3sprog or openocd may well work but I haven't personally tried either18:56
sf-slack<kgugala> you can use: xc3prog -c nexys4 /path/to/bitstream.bit18:58
sf-slack<kgugala> this works with on-board uUSB port on Arty (no platform cable required)18:59
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Xiretzaxc3sprog is exactly what I was looking for, thanks! After wrestling with broken packaging for a bit I have some pretty blinking attosoc LEDs :)19:16
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Xiretzaoh my, a fully free VHDL-to-xc7 workflow, what a time to be alive19:58
Xiretza21s from `make flash` to blinkenlights, this changes *everything* - while there's not enough functionality to synthesize the complete design I'm working on yet, it gives me huge hope for the near future :) testing anything on hardware previsouly took at least 2 minutes per run20:07
daveshahXiretza: is your design open source? If so a link to it in a GH issue would be very useful to keep in mind20:34
Xiretzadaveshah: indeed, it's a school/hobby project (simple-as-feasible rv32i core with some peripherals), I'll be sure to link it once I clean it up a bit more (have to do that anyway...). At the moment it's also still stuck on a few missing ghdl features, so not too much use for nextpnr testing.20:38
daveshahAh I see20:38
daveshahI haven't followed the ghdl side of things so much but it was improving well the least time I looked20:38
Xiretzaoh yes, tristan is an absolute beast, he almost single-handedly got the synthesis side of things to a point where it can handle most reasonable designs (I like to use all the language features I can get my hands on) - all in the last couple months20:41
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litghost> <nfrancque> Hey all.  Looking at the dsp fuzzer to get started helping out per @mithro's advice.  Anyone know if there is already a plan in place for dsp's or just keep trying to add stuff?22:34
litghostNext steps for the DSP is either:22:34
litghost1. Keep expanding the DSP fuzzer in a piece meal fashion22:34
litghost2. Write a minitest for the DSP in a useful mode, and determine what bits are still unknown.  After adding the minitest (e.g. open a PR), then focus on burning down the remaining unknown bit list22:34
litghostI've found that path #1 works well when there are a lot of bits remaining.  E.g. just trying to write fuzzers for each parameter.22:36
litghostPath #2 works well when the number of remaining bits on the DSP is lower, and you need a forcing function to drive the unknown bit count to 022:36
heijligenhey, is it possible to use the  Zynq 7000 without the PS7 ip core from xilinx? I've only managed to run either an linux on the arm cores or an bitstram (
tpbTitle: GitHub - heijligen/zynq_yosys (at
daveshahYou can use the primitive directly but it's not that fun (I'd recommend looking at the generated IP as a base)23:10
daveshahI've done similar with the UltraScale PS8 before23:10
heijligendaveshah: so looking at the verilog of the ps7 wrapper? how is the arm subsystem connectet to the fpga logic. I saw wires with names matching the ps7 documentation in the prjxray db, but I'm not so into the project to get what it means23:18
daveshahThe interface is some kind of AXI23:18
daveshahOr rather several AXI interfaces23:19
daveshahYou can find the blackbox of the primitive if you search for PS7 here:23:20
heijligenso i can use the primitives from yosys as input / output of my verilog module?23:28
heijligenis verilog case sensitive? for using with ghdl yosys ghdlsynth-beta23:29
daveshahYou can instantiate the primitive in your Verilog or VHDL23:33
daveshahVerilog is case sensitive, I'm not 100% sure how ghdlsynth handles this23:34
heijligenwhen i create an edif with yosys and ghdl my variables and signals got all lowercase23:35
heijligendaveshah: thanks for this. Great job you're doing!23:42

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