Friday, 2019-10-18

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mithromaybe someone should run on symbiflow?02:37
tpbTitle: GitHub - maximuska/depslint: A tool for dependencies validation for ninja build system using strace to detect the real dependencies (at
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hackerfoohi rajesh-s16:58
hackerfooAh, they left.16:59
tpbTitle: ECP5: Validate SerDes at 5Gbps · Issue #12 · enjoy-digital/usb3_pipe · GitHub (at
daveshahmithro: ack, will investigate over the weekend17:15
mithrodaveshah: _florent_ just said "The timings have been improved and the Host now receives correctly the TSEQ/TS1 from the Versa ECP5. I still need to look at the RX path, but we should not be far from being able to use the Versa ECP5 for the dev."18:06
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_florent_daveshah, mithro: i was expecting these timing violations, this was a first report without any optimizations. TX is now fine, RX is not far but i just spend a few minutes looking at it, i need to spend more time. The timings issue seems to be around the 8b10b decoder (which is done in the fabric), i'll probably need to do some optimizations20:12
daveshahIs there a reason you aren't using the hard 8b10b?20:13
mithro_florent_: Yeah - I was just pointing daveshah to someone doing something cool with the ecp520:13
_florent_daveshah: yes, i just want to use the serdes as simple serializer/deserializer (as we are doing with others FPGAs), and this is also useful to generate LFPS20:16
_florent_daveshah: but if it's really causing timing issues, i'll probably switch to the hard ones20:16
daveshah_florent_: ack, I think there is some OOB functionality that could be used for LFPS20:16
mankeliany idea when that ECP5 tinyfpga is coming and how much it will cost?20:17
mankelisince it has serdes, it should be capable of hdmi right?20:18
daveshahThe SERDES isn't actually a very good match for HDMI20:19
daveshahWrong signalling level20:19
daveshahIf you only need 720p60 or 1080p30, regular ECP5 IO pins are actually a better choice20:19
mankelino? I have used serdes (although friend did the ip) on zynq7 for hdmi20:20
daveshahAh, paths are crossed here20:21
daveshah"serdes" in Xilinx sense is presumably referring to IO SERDES primitives, ie still regular IO pins20:21
daveshahThere's also the high speed transceiver for PCIe, USB3, etc (GTX/GTH/etc in Xilinx)20:22
_florent_daveshah: btw, i added SCI support to have more control on the serdes parameters20:23
daveshahVery nice20:23
daveshahThat should make tuning easier20:23
mankeliit's the OSERDESE2 primitive that does the diff serial output20:24
daveshahSo the ECP5 doesn't have an exact equivalent to that20:27
daveshahBut it has ODDRX2F which is the same as an OSERDESE2 in 4:1 DDR mode20:27
daveshahUnfortunately no 10:1 or 8:1 mode20:27
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mankelithere's some document describing hdmi on ECP3 using "CML SERDES", is that something different than what the ECP5 has?20:38
daveshahAs far as I know, the only options for HDMI on ECP5 are the transceivers (Lattice call them SERDES, GTX in Xilinx world) with a level shifter; or regular IO pins and a 4:1 gearbox (SERDES in Xilinx world)20:39
daveshahBut the latter option can't do 1080p6020:39
daveshahThat app note seems to be using a level shifter20:40

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