Friday, 2019-08-09

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hackerfooGetting closer. I was able to generate rr_graph.real.xml. Now I need to fix this: PCF constraint "set_io in[0] V17" from line 2 constraints net in[0] which is not in available netlist: in, out01:42
hackerfooHopefully not too much more to go.01:43
hackerfooV17 isn't one of the pins I selected (W2/3 & V2/3)01:43
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litghosthackerfoo: What target are you running15:55
litghosthackerfoo: The current process is sdc -> ioplace15:55
tpbTitle: symbiflow-arch-defs/arch_define.cmake at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
hackerfoolitghost: buttons_basys3_x1y0_fasm15:59
litghosthackerfoo: Did you update basys3.pcf?16:04
litghostOr make a new pcf for the x1y0 test?16:05
litghostWhich?  And did you update the CMake description of the test to use the correct file?16:06
hackerfooI just modified the existing one. I'll make a separate one when it works.16:10
litghosthackerfoo: The error matches the pcf file located in master (
tpbTitle: symbiflow-arch-defs/basys3.pcf at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
litghosthackerfoo: Which path did you edit?16:12
hackerfooThat was before I modified the PCF.16:12
litghostAh, sure16:13
hackerfooStill fails the same way, though.16:13
hackerfooThe netlist is missing from the eblif, I think.16:13
hackerfooOr net.16:13
litghosthackerfoo: I'm guess, but I think it's because the new design no longer has a bus16:15
litghosthackerfoo: e.g.  input [0:0] in -> set X in, versus input [1:0] in -> set X in[0]16:16
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hackerfooI see17:28
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hackerfooNow the pads are missing from synth_tiles_pinmap.csv19:46
hackerfooI think I need to add a way of locating real pads, because they were previously synthetic tiles.19:53
hackerfooMaybe I can still add them to synth_tiles.json19:54
litghosthackerfoo: You looking for by any chance?20:10
tpbTitle: prjxray-db/xc7a35tcpg236-1_package_pins.csv at master · SymbiFlow/prjxray-db · GitHub (at
hackerfoolitghost: Thanks, that looks useful.20:11
hackerfooI'm adding code to to add an entry for each IOPAD, similar to GND & VCC.20:12
hackerfooI should probably just try changing the JSON manually first.20:13
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hzeller[m]While at it, I might be interested in U2, U4, U5, U7, U8, V4, V5, V7, V8, W4, W6, W7 :) (7-segment things in Basys3)20:31
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hackerfoolitghost: What consumes synth_tiles_pinmap.csv?23:00
tpbTitle: symbiflow-arch-defs/arch_define.cmake at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithrolitghost: I needed this patch to make the harnesses build successful....
tpbTitle: Snippet | IRCCloud (at
mithrolitghost: This look good?
tpbTitle: Comparing · SymbiFlow/prjxray-db · GitHub (at
mithrolitghost: Still looks like there is some issues with the kintex with missing IOI_LEAF_GCLK0, IOI_IOCLK0 and similar?23:53
litghostmithro: Ya, is attempting to fix it23:53
tpbTitle: Avoid failing on empty pip lists (which may occur). by litghost · Pull Request #1017 · SymbiFlow/prjxray · GitHub (at
litghostmithro: I think I have the last fix in23:53
hzeller[m]What are the premap..v verilog files generated by yosys used for ? It does not seem to be needed for the remaining vpr process (I comment them out in symbiflow-simple-sample). I suspect this is just used as a debugging output but it is not something needed in a typical workflow ? Or, in other words: can I assume that input verilog23:57
hzeller[m]output eblif is what typically is needed in a workflow invoking yosys ?23:57
tpbTitle: symbiflow-arch-defs/synth.tcl at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
litghosthzeller: The premap files can be used to feed Vivado after unmapping some VPR specific flows23:58
litghosthzeller: This allows some A/B comparisions between VPR and Vivado post-synth23:58
litghosthzeller: Going from the fully mapped output is non-trival, so we write out the verilog premapping23:59
hzeller[m]ah ok, but for just using the FOSS toolchain it is not needed23:59

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