Tuesday, 2019-07-30

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* hackerfoo sent a long message: < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/AYCHmPuYXcmghTdFxfVSTsHI >01:17
hackerfoo^ I think this is VPR's way of saying it can't route to an `.output` from the do of a slice l?01:18
hackerfooMaybe it's because I don't have enough inputs and outputs available in the new ROI.01:21
hackerfooNo, this is before that, when generating the architecture.01:36
hackerfooI'm not sure what the SLICEL has to do with .output, then.01:40
hackerfooMaybe the error message is wrong?01:43
hackerfooOh, there's a dummy design somewhere being run through VPR.01:44
hackerfooI'm not sure why it fails, but it works if I remove the single input, output, and wire.01:50
hackerfooI guess I shouldn't be surprised that things are broken enough that VPR can't route from an input to an output, but I wish it gave some sort of hint as to why.01:52
mithrohackerfoo: you can turn on verbose information on the clustering02:22
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hackerfoomithro: Thanks. I'll try setting --pack_verbosity higher.04:38
tpbTitle: vpr-20190729.txt · GitHub (at gist.github.com)04:58
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sf-slack2<acomodi> mithro: filed the issue here, the current master+wip cannot be built in conda-packages until there is a fix: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/87809:17
tpbTitle: If Graphic packages are not installed VTR build fails · Issue #878 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)09:17
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litghosthackerfoo: That error means that from the ".output" there is no pb_type routing from the blackbox to a tile pin14:41
litghosthackerfoo: Actually try disabling the pin feasibility filter14:42
litghost"FAILED Pin Feasibility Filter"14:42
litghostWe've had problems in the past where the pin feasiblity filter either was wrong, or prevent the diagnostic output that explained the failure14:42
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hackerfoo> No possible routing path from cluster-external source (LB_SOURCE) to cluster-internal sink (LB_SINK accessible via architecture pins: outpad[0].outpad[0]): needed for net 'do' from net pin 'do.out[0]' to net pin 'out:do.outpad[0]'20:36
hackerfooI don't know where `out` is coming from.20:38
hackerfooFound this in testarch.echo: interconnect 2 OUTBUF.OUT outpad.outpad20:50
hackerfoo<direct name="to_outpad" input="OUTBUF.OUT" output="outpad.outpad"/>20:52
hackerfooIt's not from there, I renamed OUT to OUT_test and that didn't change anything.20:58
hackerfooMaybe it's because the model is blank for IOPAD.21:05
hackerfooCould someone please look at https://github.com/HackerFoo/symbiflow-arch-defs/blob/x1y0/xc7/primitives/iob33m/iob33m.pb_type.xml ?22:51
tpbTitle: symbiflow-arch-defs/iob33m.pb_type.xml at x1y0 · HackerFoo/symbiflow-arch-defs · GitHub (at github.com)22:51
hackerfooI want VPR to route IOB33M.O though OUTBUF to outpad.outpad, but I must be doing this wrong.22:52
hackerfooCan it route through pb_types?22:53
hackerfooMaybe I can put inpad/outpad inside INBUF/OUTBUF.22:59
hackerfooI can get a little further by connecting IOB33M.I/O directly to inpad.inpad/outpad.outpad23:09
hackerfooBTW this is the branch I've been working on: https://github.com/HackerFoo/symbiflow-arch-defs/tree/x1y023:11
tpbTitle: GitHub - HackerFoo/symbiflow-arch-defs at x1y0 (at github.com)23:11
mithrolitghost: Did you see the following? [verilog-to-routing/vtr-verilog-to-routing] Add detailed timing report mode to VPR (#611)23:14
hackerfooNow I get this error:23:48
* hackerfoo sent a long message: < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/QrQmRZbCgILhmemdyOJMfNRk >23:48
hackerfooThere's no "switch" table in the database?23:48
hackerfooThe database is empty.23:53

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