Monday, 2019-05-27

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sf-slack2<acomodi> mithro: I have commented PR `<tile>` tags appear in XMLs (only xc7-related), but they are "invisible" to VtR08:57
tpbTitle: Sign in to GitHub · GitHub (at
sf-slack2<acomodi> mithro: more details are in the comment on GH08:57
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mithroacomodi: Okay great14:20
mithromkurc: Where are we with the Yosys attribute + parameter stuff?14:20
sf-slack2<mkurc> @mithro I fixed handling of default values of floating point (aka real) parameters14:24
sf-slack2<mkurc> So if there are no more review issues then it is ready on my side.14:25
mithromkurc: Okay I'll take a look shortly14:26
sf-slack2<mkurc> @mithro @litghost Have you managed to successfully model an async set/reset flip-flop (eg. FDSE) with timings ? I've been trying to make such a test for V2X SDF import with no success.14:47
sf-slack2<mkurc> I tried to use the exact example as given in the VPR doc (, this time no async reset and the VPR segfaults with it.14:47
mithromkurc: Example?14:48
mithroFYI it is a public holiday here in the US so litghost probably won't be around today...14:48
sf-slack2<mkurc> Ahh, ok.14:48
sf-slack2<mkurc> I can prepare a short doc with explanations / examples14:48
mithromkurc: That shouldn't be needed, just an example pasted here would be enough14:51
sf-slack2<mkurc> @mithro The example is there under the "Sequential block (no internal paths)" section.14:52
sf-slack2<mkurc> @mithro The first problem is that when such a model+pb_type is injected into the v2x test suite then the VPR crashes (segfaults) with the assertion failure: `vpr/src/timing/timing_graph_builder.cpp:250 add_block_to_timing_graph: Assertion 'clk_port' failed.`14:53
sf-slack2<mkurc> @mitrho But this is just a D flip-flop14:54
mithromkurc: I saw that issue recently14:54
mithromkurc: Let me find the fix14:55
sf-slack2<mkurc> @mitrho: Ok14:55
sf-slack2<mkurc> @mitrho And another thing: when having a FF with async set/reset like FDSE then I see no way to define timing between SR and Q.14:57
mithromkurc: It is caused by the eblif not having the clock pin14:57
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mithromkurc: that is the commit you need I think15:00
tpbTitle: mux_gen + v2x: Support generating FASM annotations for muxes. by mithro · Pull Request #703 · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithromkurc: I'll pull it out into it's own pull request15:00
litghostFdse is syncronous reset15:00
litghostFdce/fdpe is async reset15:01
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litghostIn sync case, it is clock to q timing, and setup/hold on sr15:01
litghostIn async it recovery+removal on sr15:03
tpbTitle: prjxray-db/CLBLL_L.sdf at master · SymbiFlow/prjxray-db · GitHub (at
tpbTitle: Small improvements to eblif generation by mithro · Pull Request #783 · SymbiFlow/symbiflow-arch-defs · GitHub (at
sf-slack2<mkurc> @mitrho Thanks. And yes, I meant FDCE for async reset.15:27
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mithromkurc: I added a bunch of tests into that pull request ->
tpbTitle: Small improvements to EBLIF generation by mithro · Pull Request #783 · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithrokgugala: What is the status of
tpbTitle: [DNM][WIP] Use Yosys to generate blif in v2x tests by kgugala · Pull Request #756 · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithrolitghost / acomodi: kmurry just landed the reformatting patch to vtr18:53
sf-slack2<acomodi> mithro: that's great! We need to merge it to the symbiflow fork ASAP. There already is a PR open with a merge from upstream, but currently it is failing during routing. I am looking at the issue. More information in the PR itself:
tpbTitle: Merge upstream by acomodi · Pull Request #59 · SymbiFlow/vtr-verilog-to-routing · GitHub (at
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mithroacomodi: It looks like xc7 is failing on master at the moment?19:57
mithroacomodi: Nope, I'm work sorry...19:58
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