Thursday, 2019-05-23

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tpbTitle: symbiflow-arch-defs/bram_shifter.v at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
tpbTitle: symbiflow-arch-defs/ram_shifter.v at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
hackerfooIt's the compensation needed to line up the switches and LEDs.00:03
litghosthackerfoo: That is a suprising behavior00:29
litghosthackerfoo: Sounds like we have a bug somewhere00:29
mithroacomodi: I fixed up that document00:34
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sf-slack2<acomodi> mithro: Great, thanks09:18
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litghostacomodi: Did make it to our downstream VTR fork?14:02
tpbTitle: mode selection: small fixes · verilog-to-routing/[email protected] · GitHub (at
sf-slack2<acomodi> litghost: Not yet, I'll apply them now14:04
sf-slack2<acomodi> litghost: sorry, no those are not included in our master+wip14:04
litghostacomodi: That's okay, the priority is getting the mode selection fixes upstream14:05
sf-slack2<acomodi> litghost: yep, I have noticed that the regression tests are extremely sensitive14:06
sf-slack2<acomodi> litghost: anyway I think that now everything is ok, titan benchmarks returned with very good QoRs, packing time is still even with the master14:07
sf-slack2<mkurc> I added support for importing SDF timings to V2X.
tpbTitle: Support for SDF timing import for V2X by mkurc-ant · Pull Request #765 · SymbiFlow/symbiflow-arch-defs · GitHub (at
sf-slack2<kgugala> @mithro can we bump the database so it has the latest sdfs? There were quite a few fixes merged in
tpbTitle: Merge pull request #835 from antmicro/bel-timings-fixes · SymbiFlow/[email protected] · GitHub (at
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sf-slack2<acomodi> litghost, mithro: which of the commits marked as workarounds are likely to be pushed upstream in your opinion?15:40
tpbTitle: SymbiFlow VtR Status - Google Docs (at
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tpbTitle: symbiflow-arch-defs/xc7/libraries at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
tpbTitle: GitHub - mithro/vtr-verilog-to-routing at port_bit_name (at
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mithromkurc: It'll take me a while to digest what your doing with the SDF loading in v2x...17:52
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sf-slack2<mkurc> @mitrho: I've seen your comment. So you wanted to have a flow like SDF -> Verilog -> XML ?18:08
sf-slack2<mkurc> Or to update JSON generated by Yosys with timings from SDF ?18:08
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*** adjtm has quit IRC20:30 doesn't seem to work any more on master with dram_test or bram_test22:13
hackerfooThe serial data looks fine at 500000 baud.22:14
hackerfooI don't see any recent changes, though. It must be a dependency.22:18
hackerfooThe result format got a byte shorter.22:56
litghosthackerfoo: Also possible that it is a regression23:30
hackerfooI can't find any changes to the logic. It seems that the loop count is only one byte, even though the state machine should output two bytes. The header, CR, LF are all there, and the error count is 0.23:47
hackerfooThe loop count seems to be going down, but that could just be aliasing.23:48
litghosthackerfoo: You looking at simulation?23:57
hackerfooI tried autosim. It just showed running clocks but the other waveforms were flat.23:58

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