Tuesday, 2019-05-21

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sf-slack2<acomodi> mithro: now https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/518 is complete13:48
tpbTitle: Eblif write support by acomodi · Pull Request #518 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)13:48
sf-slack2<acomodi> mithro: it correctly writes both .params and .attrs in the output blif13:48
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mithrokgugala: Your idea of using yosys on the .sim.v files is a pretty good idea15:51
sf-slack2<kgugala> @mithro I did some initial tests on that and implemented a simple python tool for updating blif generated from those sim.v files so they correspond with what the test architecture expects15:54
mithrokgugala: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/74615:56
tpbTitle: Use Yosys on .sim.v files to generate a .eblif needed for architecture testing · Issue #746 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)15:56
sf-slack2<kgugala> @mithro we have a WIP implementation of points 1 to 3 of the above issue15:58
sf-slack2<kgugala> I'll open a PR later15:58
mithrokgugala: Great!15:59
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mithromkurc: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/74816:37
tpbTitle: Add v2x to use specify section rather than the extra timing attributes · Issue #748 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)16:37
mithromkurc: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/74916:41
tpbTitle: Add support for loading timing information in v2x from SDF · Issue #749 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)16:41
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mithromkurc / kgugala: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/68116:59
tpbTitle: WIP - Tool for generating stuff related to latches by mithro · Pull Request #681 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)16:59
mithromkurc / kgugala: https://docs.google.com/spreadsheets/d/16yvScRkedOkPCRBSInFuHE_cUMD8Ls-b9KFmHocpC-o/edit#gid=017:01
tpbTitle: Flip Flops - Google Sheets (at docs.google.com)17:01
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hackerfooApparently Vivado infers the NO_CHANGE write mode for block RAM even if you specify READ_FIRST.21:05
litghosthackerfoo: There are cases where NO_CHANGE is equiv, but presumably that is an optimization?21:06
litghosthackerfoo: Read the memory guide, I believe there is a paragraph describing this behavior?21:07
hackerfooYeah, I know, I just didn't expect it to do that for me.21:07
hackerfooProbably only when you have a single write port, which is a pretty simple test.21:08
litghosthackerfoo: If I had to guess, maybe Vivado proved that write and reading over the same address was impossible, so NO_CHANGE is equiv to READ_FIRST?21:08
hackerfooOkay - It's also ignoring WRITE_FIRST? That doesn't seem right.21:10
litghosthackerfoo: If there is never a read/write address conflict, the write mode doesn't matter21:10
litghosthackerfoo: And NO_CHANGE is the least power/fastest mode21:11
litghosthackerfoo: WRITE_FIRST/READ_FIRST/NO_CHANGE have an impact if a read and write of the same address occurs in one cycle21:11
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hackerfoolitghost: Ah, DO of the write port isn't connected so it really doesn't matter.22:36
litghosthackerfoo: Right, so the mode is unobservable, in which case the cheapest/fastest mode should be used22:40
litghosthackerfoo: FYI this simple optimization (DO/DOP disconnected -> NO_CHANGE) is fairly easy to write in the techmap22:41
litghosthackerfoo: We don't have to do it at the first cut, but it isn't hard to do22:41
hackerfooI think I'm just going to keep it simple for now, and just do widths of 8/9, 16/18, and 32/36 for now, and no optimizations.22:44
litghosthackerfoo: I agree22:46
litghosthackerfoo: It seems reasonable to write a short issue with the known limitations of the current approach and what work could be done to make it complete22:47
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