Friday, 2019-05-17

*** tpb has joined #symbiflow00:00
*** space_zealot has quit IRC00:09
*** space_zealot has joined #symbiflow00:17
*** space_zealot has quit IRC02:28
*** citypw has joined #symbiflow03:46
*** proteusguy has joined #symbiflow04:18
*** Bertl_zZ is now known as Bertl05:15
*** Bertl is now known as Bertl_oO05:28
*** OmniMancer has joined #symbiflow06:07
*** citypw has quit IRC07:41
*** futarisIRCcloud has joined #symbiflow08:42
*** jevinskie has joined #symbiflow09:18
*** space_zealot has joined #symbiflow09:39
*** space_zealot has quit IRC09:45
*** jevinskie has quit IRC09:49
sf-slack2<acomodi> By checking the placement costs it is noticeable that with equivalent tiles we get a lower cost with placement. Here some data:
tpbTitle: WIP: Equivalent Tiles placement by acomodi · Pull Request #559 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
sf-slack2<acomodi> I wonder what will be the reduction when timing is added as well.10:14
*** Ultrasauce has quit IRC10:31
*** Ultrasauce has joined #symbiflow10:32
*** jevinskie has joined #symbiflow10:40
*** futarisIRCcloud has quit IRC11:01
*** jevinskie has quit IRC11:12
*** citypw has joined #symbiflow12:22
*** bjorkintosh has joined #symbiflow12:42
*** jevinskie has joined #symbiflow13:11
*** jevinskie has quit IRC13:40
*** Vonter_ has quit IRC14:06
*** OmniMancer has quit IRC14:29
*** OmniMancer has joined #symbiflow14:34
*** OmniMancer has quit IRC14:34
*** OmniMancer has joined #symbiflow14:41
litghostacomodi: Interesting!  Hopefully I'll be able to add some numbers once I get the timing stuff closing15:11
*** Vonter has joined #symbiflow15:20
*** OmniMancer has quit IRC15:20
*** Vonter has quit IRC15:41
litghost VPR can now correctly know that it produced a design that fails timing (yay!)15:50
tpbTitle: [XC7] Timing quality tracking bug · Issue #716 · SymbiFlow/symbiflow-arch-defs · GitHub (at
*** Vonter has joined #symbiflow15:50
sf-slack2<acomodi> litghost: Great! does VPR know that the clock frequency is 100MHz (for basys3)?15:56
litghostacomodi: That simply comes from the SDF (which I've hard wired for now)15:57
tpbTitle: SDC Commands Verilog-to-Routing 8.0.0-dev documentation (at
litghostSDC sorry not SDF15:57
sf-slack2<acomodi> litghost: Ok, good to know. So the issue now is that VPR is not able to find a routing with a critical path of less than 10ns, right?16:00
sf-slack2<acomodi> litghost: Or it doesn't even try again after failing?16:01
litghostacomodi: Unclear, likely this particular issue is a side affect of aggressive packing16:02
litghostacomodi: My next step is to make sure that VPR is chasing the actual critical path16:03
sf-slack2<acomodi> litghost: Got it, so you could understand if it is actually trying to solve it. Have you tried to use timing based routing and placement on designs (murax or scalable-proc) we are sure are working on HW?16:06
litghostacomodi: Ya, this is with timing based placement and routing16:07
litghostacomodi: FYI, just because something works on hardware does not mean it meets timing.  The timing analysis is examining worst case setup conditions (and hold), and on our test setups we are likely not running at the SLOW corner16:09
*** jevinskie has joined #symbiflow16:45
*** Vonter has quit IRC16:52
*** Vonter has joined #symbiflow17:09
*** jevinskie has quit IRC17:17
*** jevinskie has joined #symbiflow17:21
*** jevinskie has quit IRC17:32
elms"Simulating an FPGA with an FPGA"
tpbTitle: Our 5 Favorite Cornell University Student FPGA Projects (at
*** Vonter has quit IRC19:19
*** Vonter has joined #symbiflow19:22
*** proteusguy has quit IRC19:23
*** space_zealot has joined #symbiflow20:50
*** space_zealot has quit IRC21:02
*** space_zealot has joined #symbiflow21:03
mithroThese students have taken that concept into an existential direction by using an Intel Cyclone5 FPGA to simulate an Xilinx XC6200 FPGA.21:11
*** Bertl_oO is now known as Bertl_zZ22:09

Generated by 2.13.1 by Marius Gedminas - find it at!