Thursday, 2019-05-16

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sf-slack2<acomodi> mithro: Ok, I have pushed a simple script that makes the conversion both in the Symbiflow and VTR PRs and updated the `` script to run the conversion11:52
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sf-slack2<mkurc> Good time of day14:17
sf-slack2<mkurc> @me1 @litghost The PR for Yosys which added support for parsing Verilog attributes on parameters has been merged to the YosysHQ/master.14:18
sf-slack2<mkurc> Shall I issue a PR from YosysHQ/master to Symbiflow/Yosys/master+wip to synchronize?14:18
sf-slack2<mkurc> Or make a new PR with the same changes to Symbiflow/Yosys/master+wip ?14:19
sf-slack2<mkurc> @litghost I also updated the document regarding v2x FASM support:
tpbTitle: Google Docs - create and edit documents online, for free. (at
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litghostmkurc: PR from YosysHQ/master to Symbiflow/master+wip15:06
sf-slack2<acomodi> litghost, mithro: I have run less "massive" benchmarks to test mode selection in VTR. Interestingly the pack time is ~4% higher, but the whole vtr flow takes ~4% time less than master.
tpbTitle: Mode selection feature by acomodi · Pull Request #517 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
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sf-slack2<acomodi> litghost, mithro: moreover, I solved the issues on equivalent tiles after the upstream merge (a few things were modified by VTR devs regarding placement which affected my solution). Both the PRs (on symbiflow and VTR) should turn green15:47
litghostacomodi: Have the VTR devs responded to either PR yet?  Might be worth poking them again if they are green.16:06
litghostacomodi: > updated the `` script to run the conversion16:08
litghostDid you add a test where run_vtr_flow runs on an arch.xml which already has tiles?16:08
sf-slack2<acomodi> litghost: good suggestion, I need to add to the script a check to see if the arch.xml is already compliant with the new format16:09
sf-slack2<acomodi> CI passed on VPR reg_tests, but failed on ODIN II ones. I need to apply the architecture conversion script also in there16:18
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mithromkurc: Do you have the code / pull request for your attributes on parameters?18:01
sf-slack2<mkurc> @me1 Yes, I have the code. I didn't issue a PR. Currently it can store attributes of parameters within the RTLIL. But it can only output them to a JSON as the only backend I modified is JSON.18:19
sf-slack2<mkurc> Maybe it is a good idea to make the PR with it to Symbiflow/yosys/master+wip ?18:21
sf-slack2<mkurc> Once we agree that it has all functionalities we want we can then issue a PR to the YosysHQ18:22
litghostmkurc: Let's start the PR on master+wip and see if we can minimize impact to the RTLIL and yosys runtime.  If we can make a "zero-cost" PR for people not using parameter attributes, maybe that will be amenable18:29
sf-slack2<mkurc> Ok, then. I'll issue a WIP PR.18:30
sf-slack2<mkurc> @mithro @litghost There it is:
tpbTitle: [WIP] Support for attributes on parameters in Verilog by mkurc-ant · Pull Request #25 · SymbiFlow/yosys · GitHub (at
mithromkurc: Great!18:56
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hackerfooDoes anyone else use Emacs? If so, have you gotten it to indent Verilog nicely i.e not indenting to the open parenthesis?20:03
tpbTitle: emacs - Modify verilog mode indentation - Stack Overflow (at
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