Wednesday, 2019-05-15

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hackerfooNo, I guess not, because all these pins still need to be routed.00:01
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litghosthackerfoo: Ya, tying of nets should be done in techmap00:44
litghosthackerfoo: Word of warning on fasm2v, it currently lacks the logic to handle disambiguiating 2 RAM18E1's versus 1 RAM36E100:45
litghosthackerfoo: There is support for adding such cleanup, but because VPR didn't have RAM36E1 support, I didn't implement that cleanup step00:46
litghosthackerfoo: As far as I can tell the only difference from a FASM standpoint between RAM18E1 and RAM36E1 is how those upper address lines are routed00:46
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litghosthackerfoo: If the high address lines are tied high, than it is two independent RAM18E1, if tied to signals one RAM36E100:47
litghosthackerfoo: I don't have a good mental model of how this all works out00:47
hackerfooThat's similar to how tying A6 high keeps O5/O6 independent for two DPRAM32s.00:49
hackerfooOnce I get the 36k block working, I'll try drawing some schematics.00:50
litghosthackerfoo: If the scheme is the same as DPRAMs, that implies interesting things about the data ports which I don't think is supported by the routing.  It'll be interesting to see the schematics00:52
litghosthackerfoo: Read data ports specifically00:52
hackerfooAny idea why is RSTRAMARSTRAML called RSTRAMARSTRAMLRST in the db? It's RSTRAMARSTRAML in Vivado as expected.01:19
tpbTitle: symbiflow-arch-defs/bram.pb_type.xml at dba00415ae607c6b5768c4c3c0d2626839ecc702 · SymbiFlow/symbiflow-arch-defs · GitHub (at
litghostThat should match a wire name01:21
litghostCheck the name of the wire, rather than the port name01:21
litghostCould just be a typo!01:22
litghostI just checked, and the wire does not have that last RST01:23
hackerfooHow do I fix it?01:24
litghostPresumably that wire was never getting connected at the top level pb, so just rename the port :)01:25
litghostInteresting, I just check the generated top level pb, and it does have the post-fix01:26
litghostAh, I was look at the wrong wire01:27
litghostYou might have been too01:27
hackerfooI guess I'll just do a global search-and-replace, but it's probably somewhere in prjxray that generates the db.01:27
litghostRSTRAMARSTRAMLRST is the correct wire name01:27
litghostThe current port name is correct01:27
litghostTo show it in vivado run:01:28
litghostselect_objects [get_nodes BRAM_L_X6Y135/BRAM_FIFO36_RSTRAMARSTRAMLRST]01:28
litghostSo sorry for the confusion, but the port is actually named correctly01:29
hackerfooThen where is RSTRAMARSTRAML?01:29
* hackerfoo uploaded an image: Screenshot from 2019-05-14 18-16-06.png (8KB) < >01:30
hackerfooRight under RSTRAMARSTRAMU01:30
hackerfooThis is my design just using Vivado.01:31
hackerfooAlso, it follows the U/L naming scheme for inputs into the two halves of the RAMB36E1.01:33
hackerfooI'm pretty sure it's a typo.01:33
hackerfooI blame Xilinx for their ridiculous names.01:36
litghosthackerfoo: Oh, you are looking at the block in RAM36E1 mode01:36
litghosthackerfoo: Click the wire itself, and it will have the RST postfix01:37
litghosthackerfoo: And if you check a block in "RAMBFIFO36E1 (primary)" you'll see the port name change01:37
litghosthackerfoo: Super fun01:37
hackerfooCan you send a screenshot? I only have GLOBAL_LOGIC101:38
* hackerfoo uploaded an image: Screenshot from 2019-05-14 18-32-55.png (6KB) < >01:41
mithroduck2's first contribution as part of GSoC!
tpbTitle: Enable PugiXML compact mode by duck2 · Pull Request #51 · SymbiFlow/vtr-verilog-to-routing · GitHub (at
duck2yay :P the sax reader was much bigger, but the fastest sax parser is 3x slower than pugixml, so it kind of failed.01:47
litghosthackerfoo: You are selecting the net, not the wire or node02:21
litghosthackerfoo: Click again and it will select the node and then the wire02:21
hackerfooOkay, I'm pretty sure that's a typo on Vivado's end:03:02
* hackerfoo uploaded an image: Screenshot from 2019-05-14 19-51-49.png (16KB) < >03:02
* hackerfoo uploaded an image: Screenshot from 2019-05-14 19-53-32.png (15KB) < >03:02
hackerfoolitghost: Should we copy Vivado's typos?03:03
litghosthackerfoo: Yes03:03
litghosthackerfoo: Because it isn't a typo03:04
hackerfooWhy? What does it mean?03:04
litghosthackerfoo: The way to read it is "RSTRAMA | RSTRAML | RST"03:04
hackerfooThe U pin doesn't have the RST suffix.03:04
litghosthackerfoo: Flip through the 3 modes of the RAMB36E1 and you will see why03:05
litghosthackerfoo: Actually the way to read it is "RSTRAMARSTRAML (RAMB36E1) | RST (FIFO36E1)"03:06
hackerfooAh. Why can't they use an underscore or something?03:07
hackerfoolitghost: Is there an easy way to flip through the modes?03:16
litghosthackerfoo: Just select an unselected BRAM36E1 cell, and then select the type in site properties window03:17
hackerfoolitghost: Thanks03:34
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sf-slack2<acomodi> litghost: I would need some feedback on my comment of this issue: Does it sound correct?14:49
tpbTitle: Support Equivalent Placement Sites · Issue #513 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
sf-slack2<acomodi> litghost: mainly because I believe that the change described in the comment requires a moderate amount of effort14:51
litghostacomodi: Sorry, can you provide more context?15:03
litghostacomodi: I haven't seen a comment from the VTR dev's since 27 days ago15:03
litghostacomodi: Why not have them first look at the implementation you have done, and evaluate it15:04
litghostacomodi: Rather than preemptively conforming to another design15:04
sf-slack2<acomodi> litghost: Ok, makes sense, I wanted to explore other possible designs and see if they were implementable.15:10
sf-slack2<acomodi> litghost: in the meanwhile though I am stalled until there is a preliminary evaluation. What do you think could I focus on?15:11
litghostacomodi: If you think the suggestion in the issue is worth pursuing I won't stop you, but my understanding is we have an implementation that works.  How do the performance before/after numbers look?15:16
litghostacomodi: I would suggest ROI breakout work, e.g. VPR tiles for the clock column and IOB's15:20
sf-slack2<acomodi> litghost: ok first I will get some reports (e.g. run_time and placement cost), but I can extract those only from Symbiflow xc7 tests as equivalent tiles is supported only by those right now15:21
litghostacomodi: Oh, you need to write the arch top-level pb_type to tiles tool15:21
litghostacomodi: Did that happen?15:21
litghostacomodi: Because you should be able to run against the full suite through the tool, yes?15:22
sf-slack2<acomodi> litghost: you mean VTR test suite or the symbiflow one?15:23
litghostacomodi: VTR test suite15:26
sf-slack2<acomodi> litghost: anyway there is an initial PR with a script that moves the top level pb_types to the tiles tag (without adding the equivalent tiles though)
tpbTitle: WIP: added script to add tiles tag and equivalent tiles by acomodi · Pull Request #583 · SymbiFlow/symbiflow-arch-defs · GitHub (at
litghostacomodi: But I believe there was agreement that script needed to live in VPR?15:28
litghostacomodi: Unless your PR allows old style arch-xml's to work as is?15:28
litghostacomodi: I thought your PR required the new style tiles definition?15:28
sf-slack2<acomodi> litghost: No, the script is needed as the pb_type cannot have some child tags anymore (e.g. fc, pinlocations, ...)15:29
litghostacomodi: I think we agree that the script is needed, and it should be a part of VPR because anyone using VPR would be affected15:30
litghostacomodi: Not just symbiflow15:30
sf-slack2<acomodi> litghost: Yes indeed, in fact I do believe that it will take a while before the PR will get merged as it introduces a great change in the whole architecture definition15:31
sf-slack2<acomodi> litghost: I will add the script to VPR then15:31
litghostacomodi: I think discussing that point directly with the VTR devs is worth doing15:32
sf-slack2<acomodi> litghost: to make CI green on VPR and be able to test on all the architectures15:32
litghostacomodi: Yes15:32
litghostacomodi: There is an open question in my mind if VTR should do the top level pb_type to tile conversion internally to avoid requiring a format change15:33
litghostacomodi: But I'll let the VTR devs drive that choice15:33
sf-slack2<acomodi> litghost: you mean change all the architectures to be compliant with the new tiles concept instead of using a script at runtime?15:35
litghostacomodi: As a fallback, or something15:36
litghostacomodi: Or maybe a config flag15:36
litghostacomodi: I haven't thought my about this, I'm just trying to explore other avenues to avoid required a lot of action for endusers of VPR15:38
litghostacomodi: Overall, I would let the VRP devs guide the conversion on the breaking of backwards capability15:39
sf-slack2<acomodi> litghost: Makes sense. In fact, for now it is better to rely on a script, but it surely is something to discuss with VPR devs as you said15:43
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mithroelms: If you are okay with it, O16:55
mithroelms: If you are okay with it, I'll merge
tpbTitle: travis: Enable running scripts locally. by mithro · Pull Request #731 · SymbiFlow/symbiflow-arch-defs · GitHub (at
elmsmithro: LGTM16:56
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mithroacomodi: my preference is that we have a script which can do the conversion and only support the new format directly20:49
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