Tuesday, 2019-05-07

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mithrolitghost: We don't have a `add_file_target(FILE "xxx.py" SCANNER_TYPE python)` right?00:03
litghostmithro: We do not00:03
litghostmithro: I've thought about it00:03
mithroShould we?00:03
litghostmithro: Frankly, if we go that route, we probably should've just stuck with bazel00:03
litghostmithro: I assume you ran into a case where a target didn't rebuild because of a library?00:04
mithrolitghost: No, more I just noticed it was missing when fixing stuff for your comments...00:04
litghostmithro: The primary reason we don't have a python scanner is we don't really build any python files00:05
litghostmithro: Unlike verilog and xml's00:05
litghostmithro: So the dependency tracking is significantly weaker00:05
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mithrokgugala: You might want to look at https://github.com/SymbiFlow/symbiflow-arch-defs/pull/67203:12
tpbTitle: v2x: Run output produced through vpr by mithro · Pull Request #672 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)03:12
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sf-slack2<kgugala> @mithro, sure I'm looking into that14:29
sf-slack2<acomodi> litghost, mithro: I have re-run the test for the mode-selection on the master VTR branch (`strong_routing_mode`) and got the errors described in https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/517#issuecomment-49010397414:39
tpbTitle: Mode selection feature by acomodi · Pull Request #517 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)14:39
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sf-slack2<acomodi> litghost, mithro: could you confirm whether the first error is correct?14:40
sf-slack2<acomodi> *do you14:41
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sf-slack2<kgugala> @mithro do you want me to take a look on https://github.com/SymbiFlow/symbiflow-arch-defs/pull/672#issuecomment-490116077 ?15:05
tpbTitle: v2x: Run output produced through vpr by mithro · Pull Request #672 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)15:05
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mithrokgugala: Less for review and more for checking that things you are generating work with it15:57
litghostacomodi: Your errors look good.  Should help MohamedEldafrawy look into the issue16:00
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sf-slack2<acomodi> litghost: ok, I will provide him with all the necessary information16:04
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mithrokgugala: https://docs.google.com/document/d/1bkI14f-nvJnHIDMIdHB_nNTWToCDg8Ys_wARZHRylq4/edit16:48
tpbTitle: [Temporary] v2x stuff to merge - Google Docs (at docs.google.com)16:48
sf-slack2<kgugala> I think @mkurc should also take a look on this doc16:52
sf-slack2<mkurc> @kgugala Looking...16:52
sf-slack2<acomodi> litghost: one question, now that the split is on, is the `specialize carrychain` still required?16:52
litghostacomodi: Good question.  I don't know16:53
litghostacomodi: I think this is a case where without timing information, it is hard to evaluate the quality of output before and after16:54
litghostacomodi: I recommend we focus on getting equivilant tiles landed, and timing16:54
litghostacomodi: And after that, we can evaluate specialize vs no specialize and round robin vs no round robin16:54
litghostacomodi: I think letting result quality be our guide once we have results will help make descisions16:55
sf-slack2<acomodi> litghost: Agreed, it just popped up in my mind. For sure it is something that can be postponed16:56
litghostacomodi: Let's make sure an issue is tracking the idea16:57
sf-slack2<acomodi> litghost: I'm on it16:57
litghostacomodi: Oh, okay16:58
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mithrokgugala / mkurc: For now I think in v2x / sim.v files I think  we should use explicit mux specification rather than implicit mux inference17:25
sf-slack2<kgugala> @mithro I agree17:26
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mithrokgugala / mkurc: I added a quick section at the top on how I think we should handle all the things17:51
hackerfooI noticed read_uart.py is discarding some data, since it just reads 10KB at a time. Is it worth making read_uart.py and error_output_logic.v more robust?17:55
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hackerfoo(in arch-defs/xc7/tests/common)18:07
litghosthackerfoo: Yes/no.  I'd start with just adding the RAM32M test, and then maybe as a follow up improving error_output_logic.v18:08
hackerfoolitghost: Okay, agreed.18:09
hackerfooHas ERROR_OUTPUT_LOGIC.DATA_WIDTH(2) been tested? I'm getting 'E' right now, but read_uart.py doesn't seem to parse it because it doesn't print anything, it just happily munches all the data.18:12
litghosthackerfoo: No, but I believe DATA_WIDTH(16) is being used with BRAM18:12
litghostand DATA_WIDTH(32) I believe?18:12
hackerfooYes, in bram_sdp_test. Hmm.18:14
litghosthackerfoo: I recommend starting with18:14
litghoststty raw 500000 < /dev/ttyUSBX18:14
litghostxxd /dev/ttyUSBX18:14
litghosthackerfoo: Or redirect to a file and use xxd18:15
hackerfooYeah, I did that. That works, and I get 'E'', so I didn't want to manually parse the results to debug it.18:15
hackerfooI'm tempted to make error_output_logic.v dump ASCII hex over the UART.18:16
hackerfooAnd end records with \n.18:17
hackerfooAnyway, I should just fix read_uart.py18:18
litghosthackerfoo: I avoided bin -> ASCII because I wanted to keep resource utilization low18:18
litghosthackerfoo: But because we are fairly stable for the combintorial elements, it's probably safe18:19
litghosthackerfoo: Just make sure the bin -> ASCII is implemented as combintorial elements, and not another LUT-RAM18:19
hackerfooShould just be shifting and '0' + data[3:0]18:21
hackerfooAh, not for A-F.18:22
litghosthackerfoo: Exactly18:22
litghosthackerfoo: You should output ASCII octal18:22
litghosthackerfoo: FYI 9-scalable proc does bin -> hex18:22
hackerfooI find hex a lot easier to read.18:23
hackerfooHopefully a branch for 0-9 and A-F shouldn't be too bad.18:24
hackerfooAh, scalable_proc uses a case statement. I'll have to try that. It probably gets synthesized as a LUT.18:28
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sf-slack2<acomodi> so, with https://github.com/SymbiFlow/symbiflow-arch-defs/pull/691, xc7 CI takes ~69 minutes, not a great improvement, but it's still something20:37
litghostacomodi: :(20:39
litghostacomodi: That is an improvement of 16 minutes, so it isn't nothing20:40
sf-slack2<acomodi> litghost: well, if put in percentage it's a ~19% improvement which looks much better. let me rephrase: it is a good improvement :slightly_smiling_face:20:56
hackerfooIs it bad practice to leave inputs disconnected in Verilog if they don't matter? I know it's not good to let inputs float.22:07
hackerfooAnd if so, is it better to set them high than low?22:08
litghosthackerfoo: Disconnected is fine if they are truly don't care22:14
litghosthackerfoo: The hardware will always set them to something stable22:14
hackerfooOkay, thanks.22:14
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