Friday, 2019-04-26

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hackerfooI get these critical warnings from Vivado when using fasm2v:01:58
hackerfoo[Constraints 18-5] Cannot loc instance 'CLBLL_R_X13Y110_SLICE_X19Y110_DLUT/LUT6' at site SLICE_X19Y110,  for01:58
hackerfoobel D5LUT Routing contention at pips element DOUTMUX01:58
hackerfoo[Constraints 18-5] Cannot loc instance 'CLBLM_R_X11Y110_SLICE_X14Y110_RAM32X1D_CD/DP' at site SLICE_X14Y110, for bel C6LUT Element SLICE_X14Y110.C5LUT can not be used as a route-through for net CLBLL_R_X13Y110_SLICE_X18Y110_BMUX taged to C5LUT_O5 because a RAM or shift register is placed there01:59
hackerfooThe resulting bitstream works on hardware, though, even through the bitstream from VPR doesn't.02:00
hackerfooResolution: When using BEL constraints, ensure the BEL constraints are defined before the LOC constraints to avoid conflicts at a given site.02:02
hackerfooUsing this approach:
hackerfooI don't know what it means if Step 8 works, and yet using the *_prog target doesn't work. I guess the next step is to use bit2fasm and diff that with the previous fasm file.02:07
hackerfooOh wait - I made some changes. I'm surprise it works.
tpbTitle: WIP · HackerFoo/[email protected] · GitHub (at
hackerfooI'll have to revert them and see if it does the same thing.02:09
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sf-slack2<acomodi> I have understood what is the problem with the following error11:40
sf-slack2<acomodi> prjxray.fasm_assembler.FasmInconsistentBits: FASM line "CLBLM_R_X5Y117.SLICEL_X1.DOUTMUX.O5" wanted to clear bit (131743, 35, 21) but was set by FASM line "CLBLM_R_X5Y117.SLICEL_X1.DOUTMUX.D5Q"11:40
sf-slack2<acomodi> basically I use the `placement_index` to retrieve the right fasm name of a SLICE. The problem is that I have noticed that `SLICEL1` has the same placement_index as `SLICEL2`. So the problem raises when a CLB has both SLICES utilized and in the FASM output there will be a bit collision as `genfasm` assigns the same SLICE name to the two different SLICEs.11:43
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sf-slack2<mkurc> I made a significant progress regarding CLB tile split. Everything related to routing stored in `channels.db` seems to be remapped correctly. Now I am focusing on adapting the architecture definition to the split tiles.12:24
sf-slack2<mkurc> I managed to generate initial `arch.xml` with correct grid layout, tile types and FASM prefixes. Working on SLICE tile pb_type xmls12:50
sf-slack2<acomodi> scalable_proc with N=1 is working with equivalent tiles. I have added a temporary workaround to get the correct FASM slice name12:50
sf-slack2<acomodi> @mkurc great, I guess that we are converging to a nice tile split solution. As soon as it is done I think I will be able to remove the workarounds from genfasm12:53
sf-slack2<mkurc> Yeah, the VPR will operate only on SLICEL and SLICEM tiles.12:54
sf-slack2<mkurc> @acomodi But there is a catch with the genfasm: Right now multiple instances of eg. SLICEL have the same FASM prefix if they come from the same CLB12:55
sf-slack2<mkurc> its a matter of metadata12:55
sf-slack2<acomodi> Yes, the problem is that the metadata for a SLICE in CLBLL is different from the one in a CLBLM. The problem is that I couldn't find any clean solution to retrieve the correct metadata12:57
sf-slack2<acomodi> Actually, I am thinking that it would be better to find a solution to have a cleaner solution in genfasm anyways as it should be independent from the architecture12:58
sf-slack2<mkurc> @acomodi Maybe the metadata should travel further in the VPR flow ? I'm not familiar with how it is implemented there.13:00
sf-slack2<acomodi> @mkurc Here is a visualization of the situation: If a CLBLM is used instead of the CLBLM it will use different FASM features. The problem is that genfasm is working at the `net` level, and the `net` level is unaware of the fact that the tile have been swapped13:06
sf-slack2<mkurc> So maybe the net level should be aware of that.13:08
sf-slack2<mkurc> @acomodi BTW What is the difference between SLICEL0, SLICEL1 and SLICEL2? Why are they specialized?13:09
sf-slack2<mkurc> I must get rid of that specialization to make generic SLICE tiles13:09
sf-slack2<acomodi> @mkurc I think the reason is that in the CLB pb_type right now there are two different SLICES with two different names (even if, for instance, CLBLL has two identical SLICELs). They need to have different names otherwise VPR will throw an error13:15
sf-slack2<acomodi> But apart from that there should be no difference at all between them13:15
sf-slack2<mkurc> @acomodi You are probably right. I see that there is `ntemplate.slicelN.model.xml` file which is a template. And the only thing being changed is the `{N}` section which is present for some wire names.13:17
sf-slack2<acomodi> exactly13:17
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sf-slack2<acomodi> Morning15:33
elmsGood time of day yall15:36
sf-slack2<acomodi> I have just created a PR to add the `tiles` tag during prjxray import in symbiflow-arch-defs.
tpbTitle: WIP: Modified prjxray import to add tiles tags by acomodi · Pull Request #653 · SymbiFlow/symbiflow-arch-defs · GitHub (at
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mithroelms: Did you see ?17:17
tpbTitle: ice40: Adding real world timing values. · mithro/[email protected] · GitHub (at
elmsmithro: yeah, but then I immediately forgot about it. I'm not sure I understand the full context. Did you just mean for reference?17:20
mithroelms: Looks like I had already started importing the real timing values directly into the XML...17:21
elmsmithro: ok17:21
mithroelms: Would be good to compare to either your manual or generated version?17:22
elmsWill do17:22
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mithroelms: Happy if I merge
tpbTitle: rr_graph tests and docstrings by elmsfu · Pull Request #584 · SymbiFlow/symbiflow-arch-defs · GitHub (at
elmsmithro: I will19:29
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