Monday, 2019-04-22

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mithroMorning!14:50
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sf-slack2<kgugala> Morning15:03
sf-slack2<pgielda> Afternoon ;)15:05
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mithrokgugla: How goes the bel timing import?17:17
sf-slack2<kgugala> @mithro: I just pushed common timings merge, so now, the last step - use those in the code I implemented for arch-defs17:23
sf-slack2<kgugala> the merge is a part of this PR https://github.com/SymbiFlow/prjxray/pull/70617:23
tpbTitle: fuzzers: timings: add bel timing fuzzer by kgugala · Pull Request #706 · SymbiFlow/prjxray · GitHub (at github.com)17:23
sf-slack2<kgugala> for merging I needed the emit functionality of python-sdf-timing17:24
sf-slack2<kgugala> which was implemented over the easter weekend (+ fixed a lot of bugs in the sdf-timing lib)17:25
kgugalathere is also v2x issue with arrays of modules (listed here https://github.com/SymbiFlow/symbiflow-arch-defs/issues/595)17:29
tpbTitle: v2x features to replace XML generation · Issue #595 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)17:29
kgugalaIMO, this would have to be fixed before we can migrate from hand written xmls to the generated from verilog ones17:31
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mithroLooks like clifford is adding specify support to Yosys -> https://github.com/YosysHQ/yosys/pull/94619:12
tpbTitle: Add specify parser by cliffordwolf · Pull Request #946 · YosysHQ/yosys · GitHub (at github.com)19:12
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JuanPHello, in page https://symbiflow.github.io/prjtrellis-db/ECP5/tilehtml/PLC2.html, I don't get the meaning of E1_H02W0501 and the 1s in the F0B2 and F2B2. Are the latter some descriptive bits? Thanks19:29
JuanPI don't get the bigger picture of this19:29
daveshahE1_H02W0501 -> wire H02W0501 one to the east19:42
daveshahF0B2 -> frame 0 bit 219:43
daveshahThe 1s in F0B2, etc are the bits set to enable that connection19:43
daveshahI explain a bit here: https://youtu.be/cTOkgDZli_o19:43
JuanPThanks you Dave. I spent the whole we to review the code of Yosys, NextPNR and trellis. This is the only thing I wasn't really sure about19:45
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hackerfooDoes anyone know why RAM64M is commented out in xc7/techmap/cells_map.v?20:18
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mithrohackerfoo: So I think you want to get the "echo" files produce when running the test20:26
hackerfooFor which test? I don't see any for RAM64M.20:29
hackerfoomithro: ^20:29
mithrohackerfoo: It is a bit confusing to me why the DRAM128_DP pack-pattern is on both the DPO and SPO direct thingies...20:29
mithroThere should be a prepack file which has the molecules in it...20:33
hackerfooThanks, I found it.20:35
mithrohackerfoo: There is an interesting comment at the top of dpram128.pb_type.xml -> https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/primitives/slicem/Ndram/dpram128.pb_type.xml#L1-L720:35
tpbTitle: symbiflow-arch-defs/dpram128.pb_type.xml at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)20:35
mithrohackerfoo: It also looks like some of those comments might be wrong....20:36
hackerfooYeah...20:36
mithrohackerfoo: I think that pack-pattern is suppose to join two 128 bit LUT rams together into a molecule so that WAUSED is correctly set...20:41
mithrohackerfoo: The other pack patterns in this file seem to be called DRAM128 and DRAM128_D...20:43
hackerfooI don't see DPRAM128 in the diagram for RAM128X1D, or anywhere else in the CLB user guide. Aren't we using the same names as in the guide?20:43
mithrohackerfoo: This CL might help.... https://github.com/SymbiFlow/symbiflow-arch-defs/commit/e5a282fa7f6003dd826a6501f09be50708cff39520:46
tpbTitle: Add stubs for RAMs. · SymbiFlow/[email protected] · GitHub (at github.com)20:46
hackerfoomithro: here? https://github.com/SymbiFlow/symbiflow-arch-defs/commit/e5a282fa7f6003dd826a6501f09be50708cff395#diff-8340ba8a38e12a98b55999746e9c2eaaR57520:55
tpbTitle: Add stubs for RAMs. · SymbiFlow/[email protected] · GitHub (at github.com)20:55
hackerfooI think I need to read more before I can make sense out of this.20:55
hackerfooI'm looking at slicem.pb_type.xml, but I can't see what's out of place yet.20:56
mithrohackerfoo: What does the molecule echo file show?20:57
hackerfoohttps://gist.github.com/HackerFoo/606cbb5250263b201d6b0f7c7714d0b720:59
tpbTitle: pre_packing_molecules_and_patterns.echo · GitHub (at gist.github.com)20:59
mithrohackerfoo: The important one is that last molecule;21:02
mithrohttps://www.irccloud.com/pastebin/8V4cHWeD/21:02
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)21:02
mithrohackerfoo: pack-patterns have two usages -- they are either for21:03
mithro (a) carry chains21:03
hackerfooOkay, I'm not sure what ram0.stub is, but that seems problematic?21:03
mithro (b) Combining small parts into large parts which should be grouped together21:03
mithroThere is some info about it here -> https://vtr-verilog-to-routing.readthedocs.io/en/latest/arch/reference.html#tag-interconnect-pack_pattern21:04
tpbTitle: Architecture Reference Verilog-to-Routing 8.0.0-dev documentation (at vtr-verilog-to-routing.readthedocs.io)21:04
hackerfooThanks21:04
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mithrohackerfoo: It is unclear to me why a pack-pattern of f7a_mux stub f7b_mux makes sense...21:10
mithrohackerfoo: it is also unclear to me why someone would name something just "stub"21:11
hackerfoomithro: Yeah. I'll look into that and see where it's coming from.21:11
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hackerfooIt looks like those lines in the commit, but I'm not sure what it should be. I'll try reverting them and see what I get.21:17
hackerfooThe stub is to group the DRAMs: "To ensure that all DRAMs are co-located within a SLICE, this block is a simple passthrough black box to allow a pack pattern for dual port DRAMs."21:26
hackerfooBut I'm not sure where ram0.stub is coming from. Maybe it gets eliminated later? It's just 2 wires of output = input.21:28
mithrohttps://github.com/YosysHQ/yosys/blob/xc7mux/techlibs/xilinx/abc.box21:46
tpbTitle: yosys/abc.box at xc7mux · YosysHQ/yosys · GitHub (at github.com)21:47
mithrohttps://github.com/YosysHQ/yosys/blob/xc7mux/techlibs/xilinx/abc.lut21:47
tpbTitle: yosys/abc.lut at xc7mux · YosysHQ/yosys · GitHub (at github.com)21:47
hackerfoohttps://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/techmap/cells_map.v#L386-L388 <- stub21:50
tpbTitle: symbiflow-arch-defs/cells_map.v at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)21:50
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mithroelms: https://docs.google.com/document/d/1waqO7CYT5d9sbTKBU1-2GvFIlgRRWsusPZTYY2EfC4c/edit#22:19
tpbTitle: FASM on iCE40 - Google Docs (at docs.google.com)22:19
mithroelms: https://docs.google.com/document/d/1Zt8Jve7EA0Ieck8tAZxawcQm32Cu9oT6vQHaqaaFdOQ/edit#22:19
tpbTitle: SymbiFlow iCE40 Verilog to Routing Status - Google Docs (at docs.google.com)22:19
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mithrohackerfoo1: I logged https://github.com/SymbiFlow/symbiflow-arch-defs/issues/616 earlier23:48
tpbTitle: Rename distributed ram (DRAM) to LUT ram · Issue #616 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)23:48
mithrohackerfoo1: Are you going to log an issue about the naming and stuff?23:51
hackerfoo1Yes, I am.23:51
mithrookay great23:51
mithroWill add my 2 cents after you finish23:51

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