Tuesday, 2019-04-16

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hackerfooHow do I load the result into Vivado? I have a Verilog file and a TCL script, but "vivado -mode batch -source top_bit.v.tcl" asks me to create a project first.00:06
sf-slack2<mgielda> hi all; digging in prjxray Makefile - https://github.com/SymbiFlow/prjxray/blob/master/docs/Makefile - and admittedly not a Make master so just looking to understand some things. 1) should the "livereload" .PHONY target be "livehtml" and this is just a remnant?00:07
tpbTitle: prjxray/Makefile at master · SymbiFlow/prjxray · GitHub (at github.com)00:07
litghosthackerfoo: There is a sample script at the top of fasm2bels.py00:09
litghosthackerfoo: I can share the one I've been using00:09
sf-slack2<mgielda> 2) should the Makefile .PHONY target even be there? afaiu it should be ".PHONY help livehtml" that's all00:10
hackerfoolitghost: That would be useful, thanks.00:10
sf-slack2<mgielda> or there's some weird Makefile magic going on ;) since I want to change the Makefile there, need to understand it first00:11
litghosthackerfoo: Here, just copy in both top_bit.v and top_bit.v.tcl https://usercontent.irccloud-cdn.com/file/XfP4UpZn/test_synth.zip00:12
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elmsmgieda: looks like livereload target will run the last catch all `sphinx-build -M livereload` does that do something meaningful? (Out of touch with Sphinx)01:40
elmsmgielda: ^^01:40
sf-slack2<mgielda> $ sphinx-build -M livereload . _build/ Running Sphinx v1.7.6  Sphinx error: Builder name livereload not registered or available through entry point01:50
sf-slack2<mgielda> no, I don't think01:50
sf-slack2<mgielda> that's the commit: https://github.com/SymbiFlow/prjxray/commit/0970edb3841c5f61b855da06d062523bb618738a#diff-68a7f9edd4ffbca6adb99e2c165cfd5201:52
tpbTitle: docs: Make target for live reloading during editing · SymbiFlow/[email protected] · GitHub (at github.com)01:52
sf-slack2<mgielda> $ make livereload make: Nothing to be done for 'livereload'.01:54
sf-slack2<mgielda> ok, it's just a bug01:54
sf-slack2<mgielda> should have been livehtml01:54
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sf-slack2<kgugala> @litghost I'm looking at the F6MUX and there is no interconnect generated for this pb_type14:02
sf-slack2<kgugala> in current arch-defs we get it like that https://pastebin.com/y9PWFZpT14:02
tpbTitle: BEL_MX-F6MUX - Pastebin.com (at pastebin.com)14:02
sf-slack2<kgugala> In the pb_type generated from verilog I have https://pastebin.com/gnzS722e14:11
tpbTitle: BEL_MX-F6MUX - Pastebin.com (at pastebin.com)14:11
sf-slack2<kgugala> and vpr fails on missing interconnect14:11
sf-slack2<kgugala> Am I missing something?14:11
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sf-slack2<mkurc> @kgugala The first thing I see is that there is no `blif_model=".subckt MUXF6"` in the pb_type tag in the one generated from verilog.14:18
sf-slack2<kgugala> yes, I know that14:18
sf-slack2<kgugala> is that causing the troubles?14:19
sf-slack2<mkurc> I guess that without it the VPR will not know that it should use the pb_type for MUXF6 from the eblif file.14:20
sf-slack2<mkurc> *that pb_type14:20
sf-slack2<mkurc> https://docs.verilogtorouting.org/en/latest/arch/reference/14:21
sf-slack2<mkurc> There is a statement that for a "primitive only" pb_type the blif_model is required14:22
sf-slack2<kgugala> OK blif_model there solves the case14:23
sf-slack2<acomodi> if I am not wrong, VPR expects an `interconnect` tag as well which is not optional. If it is not present in the pb_type.xml it will fail (I think it could be empty though: `<interconnect/>`)14:26
sf-slack2<kgugala> it does not fail when blif_model is set14:27
sf-slack2<kgugala> right now I emit this https://pastebin.com/T94Dttju14:28
tpbTitle: BEL_BB-F6MUX_blif - Pastebin.com (at pastebin.com)14:28
sf-slack2<kgugala> and it passes the check14:28
sf-slack2<mkurc> I guess that the primitive pb_types do not need interconnect as there is nothing inside. They are just empty shells with pins which reference BLIF models. Though it is not stated explicitly in the documentation (at least I haven't found it).14:31
sf-slack2<acomodi> Yeah, that makes sense14:32
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litghostPrimitive pb_types are required to not have interconnect15:26
litghostAnd primitive pb_types are identified by their use of the blif_model property15:26
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tpbTitle: prjxray/kokoro-cfg.py at master · SymbiFlow/prjxray · GitHub (at github.com)16:41
elmskgugala: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/293#issuecomment-48273919116:51
tpbTitle: Improve timing model support for 7-series · Issue #293 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)16:51
sf-slack2<mkurc> @litghost There is an attribute called "ptc" in the "graph_node" table. What is it used for ?16:55
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sf-slack2<kgugala> @elms thanks17:01
sf-slack2<kgugala> Those asterisks in PLL's do look like spec violation17:02
litghostmkurc: It is overloaded, but for CHANX and CHANY it is to assign visual locations in the VPR renderer.  ptc's are handled automatically via the channels2 code17:02
tpbTitle: symbiflow-arch-defs/prjxray_create_edges.py at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)17:02
sf-slack2<mkurc> @litghost Ok, thanks17:03
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litghostkgugala: Do you want me to take a crack on solving the v2x/ntemplate dependency?  Or do you have most of a solution ready?17:21
sf-slack2<kgugala> I'll take a look on that today. I need to understand that if I'm about to implement the whole arch.xml generation from verilog17:23
hackerfoolitghost: I ran the script and got this error: ERROR: [Vivado 12-2285] Cannot set LOC property of instance17:25
hackerfoo'CLBLM_L_X10Y125_SLICE_X12Y125_RAM32X1D_CD',  for bel C6LUT Element17:25
tpbTitle: log.txt · GitHub (at gist.github.com)17:25
litghosthackerfoo: Must be a bug in the fasm2v annotations.  Check what the placer is doing versus what VPR did17:27
litghostkgugala/acomodi: Are either of you planning on fixing up https://github.com/SymbiFlow/symbiflow-arch-defs/pull/316 today?  If not, I can do that so we have a base to extend the v2x tests17:30
tpbTitle: WIP: Improve the Verilog to XML conversion process by acomodi · Pull Request #316 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)17:30
sf-slack2<acomodi> litghost: I can take a look on that and fix all. I will probably squash all the commits in chunks to make thinks clearer17:36
litghostacomodi: Agreed, sounds good17:36
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hackerfooI got it to finish without errors by ripping out the UART and ERROR_OUTPUT_LOGIC in ram_test.v.18:23
hackerfooAlthough it generated a bad line in the TCL script: set_property FIXED_ROUTE [list  ] $net18:24
hackerfooSo I commented that out. I'm going to see if I can fix it.18:24
mithrolitghost: Do you have a solution for the carry4 stuff in the slicel? https://github.com/mithro/symbiflow-arch-defs/blob/8ce13bac25af2dab1203558aa03dc344c80c61ac/xc7/primitives/common_slice/common_slice.sim.v#L181-L186 ?19:24
tpbTitle: symbiflow-arch-defs/common_slice.sim.v at 8ce13bac25af2dab1203558aa03dc344c80c61ac · mithro/symbiflow-arch-defs · GitHub (at github.com)19:24
mithrolitghost: Need to replace it with the carry0 and carry with split fabric primitives19:24
litghostmithro: Ya, it needs to be carry0 and 3 carry's19:25
mithrolitghost: Did you want to do that while I grab lunch, or should I do it when back?19:27
litghostmithro: Go ahead and do it19:27
mithroI'm going to grab some lunch first I think19:28
mithroBe back in 1519:28
litghostmithro: I will say that the slicel.sim.v needs a lot of work to actually match the xml19:28
litghostmithro: And there are missing features in v2x to actually output the current XML19:28
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mithrolitghost: What apart from fasm + pack patterns?19:57
litghostBig feature that is missing is multiple copies of a model19:57
tpbTitle: v2x features to replace XML generation · Issue #595 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)19:57
sf-slack2<kgugala> @litghost @mithro yeah it hit me too19:58
sf-slack2<kgugala> this is a serious issue19:58
litghostkgugala: I was waiting util the other v2x stuff lands19:59
litghostkgugala: In particular the depedency work you are doing and the PR that acomodi is fixing up19:59
sf-slack2<kgugala> I think dependency should be ready soon19:59
sf-slack2<acomodi> litghost: I am currently fixing the PR, just pushed a cleaner version19:59
litghostacomodi: Okay, thanks20:00
mithrolitghost:  I thought I had a fix for that somewhere...20:00
sf-slack2<acomodi> litghost: I still need to go through your comments on the PR and fix them now20:00
litghostacomodi: Okay20:01
sf-slack2<acomodi> litghost, mithro: there is one thing though that I should fix which is the direct connections generated from v2x that I have modified 3 months ago https://github.com/SymbiFlow/symbiflow-arch-defs/pull/18320:02
tpbTitle: Rework the XML format for pb_type to better allow composition by mithro · Pull Request #183 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)20:02
litghostIt's unclear the value of https://github.com/SymbiFlow/symbiflow-arch-defs/pull/183 given that we are planning on generating everything20:04
tpbTitle: Rework the XML format for pb_type to better allow composition by mithro · Pull Request #183 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)20:04
sf-slack2<acomodi> in that PR, which is now closed, was stated that the `direct` connections should change from `<direct input="XXXX.CLOCK_ENABLE" output="in_cen.EN" name="XXXX">` to `<direct><port name="CLOCK_ENABLE" type="input"/>  <port name="EN" type="output" from="in_cen"/></direct>`20:05
litghosthttps://github.com/SymbiFlow/symbiflow-arch-defs/pull/183 removes redundancy at the cost of hurting readability20:05
tpbTitle: Rework the XML format for pb_type to better allow composition by mithro · Pull Request #183 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)20:05
mithroWell yosys now passes the slicel.sim.v model!20:06
sf-slack2<acomodi> Yep, should I leave the things as they are right now (input and output are not in separate tags) then?20:06
mithrobut netlistsvg fails on the constants...20:06
litghostIn addition the new syntax I don't believe handles arrays of modules20:06
litghostacomodi: Leave the direct connects as they are20:06
sf-slack2<acomodi> litghost: all right20:07
mithrofile:///usr/local/google/home/tansell/github/SymbiFlow/symbiflow-arch-defs/build/xc7/primitives/slicel/slicel.bb.svg https://usercontent.irccloud-cdn.com/file/myqiYNtS/image.png20:19
mithroNot the best layout....20:20
litghostFYI, the first carry should be CARRY020:21
litghostand the PRECYINIT mux doesn't match the XML structure20:21
mithrolitghost: Yeah there are some issues -> file:///usr/local/google/home/tansell/github/SymbiFlow/symbiflow-arch-defs/build/xc7/primitives/slicel/slicel.flat.svg https://usercontent.irccloud-cdn.com/file/x6n6XWd9/image.png20:24
mithrolitghost: Where does CARRY0_CONST goes where?20:27
litghostroot of the chain20:28
litghostin the SLICE20:28
litghostJust look at the XML20:28
mithrolitghost: Oh, I see why muxgen isn't used as much anymore20:41
mithrolitghost: Also, it seems PRECYINIT_MUX just connects AX to CI_INIT ?20:41
litghostlitghost: Ya, C0 and C1 are now handled in synthesis20:42
litghostmithro: And treated as parameters, rather than routed20:42
litghostmithro: I could add them back as constant sources in the pb_type, but I'm following the principle, if you can do it in synthesis, do that20:42
sf-slack2<acomodi> litghost, mithro: I have checked the status of the v2x PR (https://github.com/SymbiFlow/symbiflow-arch-defs/pull/316) I have noticed that some v2x tests will fail if some assertions are not commented out. I guess that when we have green travis we should merge the PR and then work on solving the issues to the tool.20:50
tpbTitle: WIP: Improve the Verilog to XML conversion process by acomodi · Pull Request #316 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)20:50
litghostacomodi: Let's get a green CI on merge, and put commented out tests in an issue with a fix list20:51
mithrolitghost: Getting closer? https://usercontent.irccloud-cdn.com/file/UGDVGxZq/image.png20:55
litghostCO_FABRIC should do somewhere20:55
sf-slack2<acomodi> litghost: how to automatic reformat in arch-defs? I got this in travis CI https://pastebin.com/4CWkkjnv20:58
tpbTitle: Scanning dependencies of target check_python yapf needs to reformat /home/travi - Pastebin.com (at pastebin.com)20:58
litghostmake format_python20:58
sf-slack2<acomodi> right, thanks20:59
mithrolitghost: I think we should add `make format` which runs `make format_python` and the others...21:03
litghostmithro: Sure21:03
litghostmithro: I believe elms was working on a PR to format other types that does that21:03
sf-slack2<acomodi> i got some files which are not related to v2x formatted as well21:03
sf-slack2<acomodi> should i just add them as well in your opinion?21:03
litghostacomodi: That is a side affect of a yapf change21:03
mithroacomodi: Check your yapf version -- see pull request for litghost21:04
litghostacomodi: Merge with master21:04
mithrobe back in 30m21:04
sf-slack2<acomodi> Ok21:04
sf-slack2<acomodi> litghost: now `testarch presubmit` completes successfully on CI, I expect the same to happen for the others. I've pushed format corrections and hopefully CI will be green on everything21:18
litghostPlease address https://github.com/SymbiFlow/symbiflow-arch-defs/pull/316/files#r275509720 and also modify the CI scripts to build the v2x tests21:20
tpbTitle: WIP: Improve the Verilog to XML conversion process by acomodi · Pull Request #316 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)21:20
litghostI guess you added https://github.com/SymbiFlow/symbiflow-arch-defs/pull/316/files#diff-782ab5f76515b2b0ae739890283333a2R58 to "all" so the all target will run them21:21
tpbTitle: WIP: Improve the Verilog to XML conversion process by acomodi · Pull Request #316 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)21:21
litghostacomodi: Assuming CI is green, please address the remaining PR comments.  They are pretty small21:23
sf-slack2<acomodi> So, actually for the time being I have disabled the whole `tests` directory21:23
sf-slack2<acomodi> Yep, I am on it21:23
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litghostacomodi: Why tests?  It was working on the previous master?21:24
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litghostAh, you mean utils/vlog/tests21:25
litghostNot tests21:25
sf-slack2<acomodi> yep, sorry utils/vlog/tests21:25
sf-slack2<acomodi> they have been added with #316 PR. I suggest that for now we wait for green CI and merge. And think about its solution afterwards. I have opened a ticket for that already. I'll solve the other changes to be done not related to the vlog tests and I think it could be good to go21:27
mithroBack now21:40
hackerfooIs there a way to feed a clock signal into clk during simulation in Vivado? Or should I generate my own clock.21:47
mithrohackerfoo: I think you have to generate your own21:47
mithrohackerfoo: Maybe ask on ##openfpga?21:47
sf-slack2<acomodi> litghost: done, ice40 previously failed, but it was for an http issue while downloading conda21:48
litghosthackerfoo: I usually just force it21:48
litghosthackerfoo: Right click the clk and then "Force clock ..."21:49
mithrolitghost: Is there a way we can make cmake symlink the files into the build directory?21:49
hackerfooThanks, I just found that.21:49
litghostmithro: Currently we use https://cmake.org/cmake/help/v3.2/manual/cmake.1.html#command-line-tool-mode in copy mode21:50
tpbTitle: cmake(1) CMake 3.2.3 Documentation (at cmake.org)21:50
litghostmithro: There is https://cmake.org/cmake/help/v3.2/manual/cmake.1.html#unix-specific-command-line-tools, but it is unix/linux only21:51
tpbTitle: cmake(1) CMake 3.2.3 Documentation (at cmake.org)21:51
mithrolitghost: So they should be copied into the build directory?21:56
litghostmithro: Can you reprahse?21:56
mithrolitghost: I have an autolinter running on my editor, if I open a file in xc7/primitives/... it gets all angry about missing includes (for the auto-generated files). If I open it in build/xc7/primitives/.. it gets overwritten every build...21:58
litghostmithro: Yes21:58
litghostmithro: What's the question?21:59
mithrolitghost: If it was a symlink instead then I could open it in build/xc7/xxx and but it would actually be changing the xc7/xxx file...21:59
litghostmithro: Yes, but it would only work on linux21:59
mithrolitghost: I don22:00
litghostmithro: https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/make/file_targets.cmake#L26322:00
tpbTitle: symbiflow-arch-defs/file_targets.cmake at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)22:00
mithrolitghost: I don't know we support anything but linux at the moment?22:00
mithrolitghost: Would it be okay if I made that an option to do linking?22:00
litghostmithro: Sure22:00
litghostmithro: I don't mind22:01
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hackerfooI'm getting 502s errors from Conda on Kokoro: CondaHTTPError: HTTP 502 BAD GATEWAY for url <https://conda.anaconda.org/symbiflow/noarch/repodata.json>23:07
hackerfooShould I just restart it somehow?23:07
hackerfooOr just merge since it's pretty minor: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/60023:09
tpbTitle: Fix typos in clb_models.py affecting the RAM32X1D LUT mode by HackerFoo · Pull Request #600 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)23:09
litghostYa restart23:11
litghostThere is a kokoro tag "kokoro:force-run"23:11
litghosthackerfoo: In your case, do wait for travis, because it's checking for python formatting23:12
mithrolitghost: Why is it CARRY0_CONST and not CARRY0 ?23:36
litghostCARRY0 is the thing we get out of the yosys techmap23:37
litghostCARRY0_CONST handles the constant bits23:37
mithrolitghost: So CARRY0_CONST isn't used in the pb_types at all?23:41
litghostCARRY0 isn't used, CARRY0_CONST is23:41
litghostJust look at the XML, https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/primitives/common_slice/carry/carry0.pb_type.xml#L123:41
tpbTitle: symbiflow-arch-defs/carry0.pb_type.xml at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)23:41
litghostWell I guess you have to look carefully, the pb_type name is CARRY0, the subckt is CARRY0_CONST23:42
mithrolitghost: Oh - I see what is going on, the carry0.sim.v isn't in the CMakelists.txt file...23:50
litghostmithro: And isn't used23:50
hackerfooI tried removing all connections to O5 in the model and pb_type for dpram32, but ram_test still doesn't work on hardware. So that isn't the problem.  It must just be the routing, but I can't find a good way to check that things are routed properly.23:51
hackerfooI think I might just route everthing to switches and lights on the board.23:52
litghosthackerfoo: That's what the test in xc7/tests/dram does23:53
litghosthackerfoo: And how I debugged RAM64X1D to begin with23:53
hackerfooI wish I had just stuck with that from the start. Maybe. If I can figure it out that way.23:54

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