Friday, 2019-04-12

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hackerfooNone of this explains why 32X1D doesn't work in VPR, right? I think I need to look at the routing.00:03
litghosthackerfoo: True, VPR should be able to pack 1 of them (instead of both)00:03
litghosthackerfoo: Check which address lines were being used00:03
litghosthackerfoo: The high bit should be unused00:04
litghostmkurc: I've got top_bram_n2 in Vivado simulating, and I'm starting to debug it.  I can see that the fsm_pulse_cnt isn't incrementing, but debugging is going pretty slow00:05
litghostmkurc: If you want a break from the tile split, would probably accelerate debugging the scalable proc failure00:05
tpbTitle: Improve xc7 fasm2verilog output · Issue #578 · SymbiFlow/symbiflow-arch-defs · GitHub (at
hackerfooAlso, di comes in DX & CX, while di2 comes in DI, so no need for BI.00:10
hackerfooWhich wouldn't work because BLUT isn't being used.00:11
* hackerfoo posted a file: dram2.jpg (126KB) < >00:15
litghostI think vpr was packing the second ram into blut which is legal00:15
hackerfooD6 and C6 aren't connected.00:15
hackerfooYes, VPR is using a suboptimal but (I think) correct configuration, so the problem must be elsewhere.00:17
hackerfooHow do I override Conda? I want to add RAM32X1D to cells_sim.v in Yosys.01:26
litghostSet YOSYS env var01:33
litghostin general capital binary name as an env var will override conda01:33
litghostI generally use YOSYS VPR and GENFASM01:34
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hackerfooOverriding the binary doesn't affect the techlibs path, unfortunately.03:25
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sf-slack2<mkurc> @hackerfoo You can navigate to the Conda env. directory and make change to the techmap there. Its under build/conda I guess06:05
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sf-slack2<mkurc> @litghost I've updated the VPR to the most recent master+wip (all the time I was using an "old" one). And now everything routes correctly when I shift the grid in X direction.07:54
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litghostMkurc: ah, very good13:10
sf-slack2<mkurc> @litghost I've cleaned the code formatting and pushed everything. There is a "fake" CLB split implemented there which converts each CLB to a CLB + EMPTY (NULL) tile. And it works.13:15
hackerfoomkurc: I'm afraid that if I modify anything managed by Conda it will get overwritten. Of course I could copy it over again, but I don't want to fight the build system. I was able to get what I wanted for now by manually running the simulation.13:24
sf-slack2<mkurc> @hackerfoo As long as you do not delete the build folder or touch yosys binary in there, techmaps will not be overwritten.13:26
sf-slack2<mkurc> You can make experiments there provided that you will remember to back them up.13:27
litghosthackerfoo: Ya.  FYI yosys has a way to understanding the share folder with the '+/...', but iverilog needs the full path15:06
litghosthackerfoo: We could add logic to handle redirecting the CELLS_SIM variable based on the YOSYS env var15:06
tpbTitle: symbiflow-arch-defs/arch_define.cmake at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
litghosthackerfoo: Ah, I thought of this15:07
tpbTitle: symbiflow-arch-defs/env.cmake at aee4d6aea05a88bc5cae1d50ff695ff3e86962ad · SymbiFlow/symbiflow-arch-defs · GitHub (at
litghosthackerfoo: YOSYS_DATADIR is a CMake cache variable, it can be overridden15:07
litghosthackerfoo: Default is to point to conda15:07
litghostmkurc: Great news, I'll try to review the PR today.15:08
hackerfoolitghost: Thanks15:09
sf-slack2<mkurc> @litghost I am trying to run a `*_autosim_bit` target and the `fasm2bels` complains that it cannot find the `xc7a35tcpg236-1_package_pins.csv` file. Any idea where can I get (or build) this file ?15:13
litghostmkurc: needs to be merged15:13
tpbTitle: Bump third_party/prjxray-db from `e6837b7` to `d31753b` by dependabot · Pull Request #581 · SymbiFlow/symbiflow-arch-defs · GitHub (at
litghostmkurc: Let me do that now15:13
litghostmkurc: Rebase/merge from master, and that should be fixes15:14
sf-slack2<mkurc> @litghost Thanks15:14
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sf-slack2<acomodi> update on tile_equivalence: I have created a script to move the tile relative tags/attributes to the tiles tag in the XML, it still is WIP as it is specific to the xc7 architectures and it cannot handle generic architectures, I'll open a PR shortly15:45
sf-slack2<acomodi> moreover, I am currently building picosoc with the equivalence tiles enabled, the process reached the routing stage and is currently at the first iteration.15:46
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sf-slack2<mkurc> @litghost / @me1 I have the tool for traversing the rr graph. Its written in C++. Shall I create a PR with the code to symbiflow-arch-defs? Where shall I put it in the folder structure ?16:04
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mithrokgugala: Morning?16:26
sf-slack2<kgugala> Morning16:27
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litghostmkurc: Any reason to not write the tool in python?   Symbiflow-arch-defs is mostly written in Python, and I don't see a strong reason to have it in C++.  Would you mind converting it, if it is not too much trouble?16:40
litghostmkurc: As for location <root>/utils is a good place for it16:41
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mithroDoes anyone know the status of ?16:52
tpbTitle: Rename pip to int fuzzers · Issue #484 · SymbiFlow/prjxray · GitHub (at
mithroJust FYI - VtR just merged -- "Packer: Added support for architectures with more than one chain per cluster (#529)"16:55
litghostmithro: Hasn't been done16:55
mithroFor some reason kokoro doesn't seem to want to run on the dependabot pull requests :-/17:00
litghostmithro: I noticed that too17:01
litghostmithro: Thought I was missing something17:01
mithrolitghost: It only automatically runs on people who are team members or collaborators (or when one of those people adds the kokoro-run label)17:01
mithrolitghost: But I can't seem to figure out how to convince kokoro that dependabot is a real person due to the fact it is a "GitHub app"17:02
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litghostmithro: What about having dependabot add the kokoro-run label?17:02
litghostmithro: Is that easier?17:02
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mithrolitghost: Well, if dependabot added the kokoro-run then I think it would still be ignored because its still an untrusted user?18:26
litghostmithro: Ah :(18:26
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sf-slack2<acomodi> update on equivalent tiles: Routing of picosoc completed successfully as well as the consistency check18:38
sf-slack2<kgugala> Awesome18:42
litghostacomodi: Great!18:53
mithroacomodi: Cool!18:56
mithrolitghost: Your Yosys change was merged20:34
litghostmithro: Ya, I need to merge yosys in our downstream branch20:34
litghostmithro: I'm trying to debug
tpbTitle: Router generating "stub" or "antenna" nets · Issue #526 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at
litghostkem_ provides a commit that in theory should report stubs, but it doesn't report anything20:35
litghostWhich is actually interesting, but did the analysis and showed that there was20:35
litghostbecause I did the analysis and showed that there was20:35
litghostSo either there is a bug in kem_'s check, or something else is going on20:36
mithrolitghost: You suggested that maybe something isn't being emitted or loaded correctly?20:43
litghostmithro: Don't know anymore.  I think there may be a bug in the FASM edge emission code, still investigating20:44
litghostmithro: Because the FASM definitely has stubs20:44
litghostmithro: But if the VPR routing graph doesn't, then something is misisng20:44
mithrolitghost: Yeah20:44
litghostmithro: I haven't proven where the problem is just yet, but if I'm correct that the VPR routing graph has no stubs, but the FASM output does have a stub, then we have a bug that could totally explain
tpbTitle: [XC7] Some designs fail on hardware · Issue #491 · SymbiFlow/symbiflow-arch-defs · GitHub (at
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mithrolitghost: I guess that is good?21:47
litghostmithro: That we have a lead?21:47
mithrolitghost: Yeah21:47
litghostmithro: Anyways, I think kem_'s code is just wrong21:47
litghostmithro: I'm trying a new algorithm to see if kem_'s stub checking code is broken21:48
litghostmithro: Ya, I think I've proven to myself that kem_'s stub detection was broken, so that avenue of thought is down22:15
litghostmithro: Back to figuring out what is wrong from the fasm2v output :/22:16
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