Thursday, 2019-03-28

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sf-slack<tmichalak> Hello everyone, I was looking into the last obstacle that keeps us from entirely getting rid of the harness design.bit in the symbiflow-arch-defs, namelly some bits missing in zynq7 ( I posted my crosscheck in the issue. Seems that we are missing few bits for CLK_BUFG_REBUF, RIOB33 and RIOB33_SINGLE. Maybe we could change the harness design to use only the RIOB bits11:39
sf-slackwe already solved?11:39
tpbTitle: unknown bit in zynq7 harness · Issue #746 · SymbiFlow/prjxray · GitHub (at
sf-slack<tmichalak> There is also one bit that I haven't seen before, namely there is no segment in the tilegrid.json with this baseaddress that has more than 28 frames and the minor address in this case is 2911:41
sf-slack<tmichalak> @litghost: About the GFAN fuzzer, I saw one commit of yours (  which reverts the MAKETODO_FLAGS so that the 054-pip-fan-alt fuzzer only solves the FAN_ALT.GFANs. Before the revert it solved BYP_ALT.GFANs as well. Maybe this  is a regression that is causing conflicts mithro spotted:11:47
sf-slack ?11:47
tpbTitle: Revert 054 fuzzer. · SymbiFlow/[email protected] · GitHub (at
tpbTitle: INT FAN_ALT[0-9].GFAN0 solutions are still unstable · Issue #567 · SymbiFlow/prjxray · GitHub (at
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sf-slack<mkurc> I've added support for explicitly instantiated DRAMs to the `tests/9-scalable_proc` design. This will allow Symbiflow bitstreams to be processed by `fasm2bels` which currently has problems with BRAMs.
tpbTitle: Selectable ROM implementation (BRAM or DRAM) for the "9-scalable_test" design by mkurc-ant · Pull Request #510 · SymbiFlow/symbiflow-arch-defs · GitHub (at
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sf-slack<acomodi> litghost, mithro: I have started to deal with the equivalent tile type implementation in VPR. There still are some unclear parts which are probably pushing me in the wrong direction. First of all I need to analyze how the placer works and what information it gets from the packer to perform the task.14:16
litghostacomodi: I strongly suggest you write up your plans e.g. light design.  The you can share it with mithro, the vtr devs and myself14:19
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sf-slack<acomodi> litghost: Ok, I have started writing a doc, but I still need to understand how and what are the VPR parts that will be affected by this feature as currently there is no reasonable plan that I could write up14:26
litghostacomodi: Sure.  vtr-dev's (once it is not finals season) might be able to provide useful guidance14:26
sf-slack<mkurc> @litghost: I added a section "Proposed algorithm" to the document describing the grid split. Could you look at it and tell whether this is a correct approach. I summed up all necessary steps there regardless of how they are to be implemented.14:28
tpbTitle: Google Docs - create and edit documents online, for free. (at
litghostmkurc: I've summarized which steps are unnecessary.14:37
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sf-slack<mkurc> @litghost: Thanks.16:34
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dhiraj240hello, i had commented on and this is my PR
tpbTitle: Make satsify pep8 · Issue #14 · SymbiFlow/symbiflow-arch-defs · GitHub (at
dhiraj240I haven't got any reply, i apologize if i have committed something wrong from my part.18:54
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elmsmitho: litghost: In the past we have used yapf exclusively. This is a formatter only. Do we also want a linter running on our python?20:59
litghostelms: I use a linter personally.  I don't think we want to fail CI on lint, I'd rather rely on unittests.21:00
litghostelms: I currently use pyflakes21:01
elmslitghost: I know you have given me feedback on things a linter would catch. So if we are going to expect that we should integrate it as a pre-submit step.21:03
elmsmithro: ^^ apparently I can't type your nick correctly21:03
litghostelms: Example?  Are thinking of naming convention errors?21:06
elmslitghost: yes and I think maybe unused imports21:06
mithroelms: I'm always confused between the different internal Yosys names21:15
elms+mithro I agree but not sure a manual list is maintainable. Maybe if descriptions are integrated with yosys. We can generate gate level schematics...or I have seen those at some point. Not sure if that would help elucidate though.21:17
mithroelms: We could move to generating the Yosys output from the spreadsheet?21:18
elmsmithro: not sure what I was expecting the '+'21:18
elmsmithro: yeah maybe21:18
mithroelms: You can export the spreadsheet as JSON pretty easily21:18
elmsmithro: probably worth mapping it out manually and then figuring a solution after the info is captured in once place.21:19
elmsmithro: Any thoughts on a using a python linter?21:20
mithroelms: We should use yapf atleast...21:20
elmsSo that formats and I have a local change to do that. But I was thinking a stronger linter to check for naming convention and unused variables/imports etc.21:21
mithroelms: Yeah, pyflakes isn't bad21:34
tpbTitle: VtR Python API Design Doc - Google Docs (at
litghostmithro: I was able to completely replicate the constant routing graph issue in the testarch, case for case.  mux and short's both fail by default, and mux with high bb_factor succeeds, and short with high bb_factor fails22:54
litghostmithro: Please review , I have two PR's after it to get to the failing test case22:55
tpbTitle: Add 10x10 test arch and add const sources. by litghost · Pull Request #515 · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithrolitghost: so I think you have two bugs right?22:56
mithrolitghost: one for the short with high bb_factor failing22:57
litghostmithro: E.g. change how we generate the constant grid and explore why VPR isn't finding a route?22:57
litghostmithro: Ah sure, yes.  The bb_factor should've helped the short case, but it didn't22:57
mithrolitghost: one for this not working with low bb_factor?22:58
mithroJust waiting for a bus, will look at when on the bus22:58
litghostmithro: Right.  For now I'll keep them in one VPR issue and we can split them if the vtr-dev's want to22:58
litghostmithro: I noticed we never connected the carry chain on the testarch, should I add a PR to do so?22:59
mithro Well, the first issue is clearly a bug that should be fixed - the second requires a bunch more thought?22:59
litghostmithro: It's not clear to me how much this represents a bug in how we generate the channels in the rrgraph versus a bug in the router23:00
litghostmithro: I'd like the vtr-dev's to make a call around that23:01
mithroThe first issue about short verse mux is just a straight bug?23:01
mithroThey should behave the same in this case I'm pretty sure...23:01
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litghostmithro: For, do you need me to resolve the "too many variations in the test arch problem"?  I'm not sure it has a good answer.  I am planning to remove the old cgen stuff before merging23:21
mithrolitghost: No23:22
mithrolitghost: Removing the cgen stuff would probably be good23:22
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mithrolitghost: I did a quick braindump of areas I was exploring with the testarch stuff ->
tpbTitle: Test Architectures - Exploring Options - Google Docs (at
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litghostmithro: is the next PR for the constant routing stuff.  The PR after this adds the global constant routing network23:46
tpbTitle: Convert testarch to graph2 library. by litghost · Pull Request #516 · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithrolitghost: If I understand the issue correctly, the problem is this ->
tpbTitle: vpr bb_box issue with rr_graph - Google Drawings (at
litghostmithro: Turns out u-turn is not required.  The example in the test arch only has the cross-bar global network, and it is still enough to trigger the bug.23:51
litghostmithro: Simply by virtue of putting the cross bar outside the ROI breaks the mux case23:52
litghostmithro: In the short case, I need to look deeper, but I believe the router is taking the N rather than N-1 channel, and then stops23:52
mithrolitghost: That second section make sense?23:55
litghostmithro: Correct23:56
litghostmithro: The one thing to added is that there is another channel path that lies in between, but because the IPIN is only on the LEFT (or RIGHT), only one of the two channels is a "good" path23:56
litghostmithro: I'm not totally sure, but I believe this channel that lies on the other side of the tile, but is not connected, is what is "breaking" the short case23:57

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