Tuesday, 2019-03-19

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duck2i poked around with sax parsing01:22
duck2it's not possible to do right away due to the edge->switch->node dependency01:26
litghostduck2: How so?01:34
duck2but it's possible to first incrementally read into a "raw rr graph" struct, then use the struct to build graph. this is very much like flatbuffers so i'm hesitant to do it, but i think at the worst case i'll have made a tool to convert large rr graphs to flatbuffers?01:34
litghostduck2: Can you create an issue on https://github.com/SymbiFlow/vtr-verilog-to-routing and explain your finding with SAX?01:35
tpbTitle: GitHub - SymbiFlow/vtr-verilog-to-routing: SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research (at github.com)01:35
litghostduck2: Because I'm not following why the edge->switch->node issue would be a problem01:36
litghostduck2: I think it is safe to assume that edge's will appear after switches and nodes, and you could always do some kind of deferal on the off change that isn't true01:36
duck2litghost: by "right away" i mean just stuffing data into device_ctx as it comes01:36
litghostduck2: I think we can just assert that edges must come after nodes and switches, does that solve what you are thinking about?01:37
duck2i think it does. if nodes, switches and edges appear in this order, the reader won't have to cache much data01:38
litghostduck2: The XML writer for VPR always writes switches before nodes and nodes before edges01:39
litghostduck2: And you could always have a dual path in the parser, seen switch+node -> insert edge immediately, not either switch/node -> put edges in a vector and then insert the edges into the nodes.01:40
litghostduck2: Maybe file an issue with the upstream project and ask if it is safe to assume the order of tags01:40
duck2what would be a "maximum" size of a rr_graph.xml?01:56
litghostduck2: billions of edges?01:57
litghostduck2: Like really really big01:57
duck2i'm asking this to know if the "raw graph" struct can be a problem. whereas eliminating the struct would save up some more memory, having it would be very helpful because both the current reader and your flatbuffers reader assume a "reference structure" in memory02:01
duck2i'm afraid if i rewrite the reader fns for reading in a single pass(for instance, process_seg_id() looks up segments for every node after everything is loaded), i might create a rather buggy version02:02
duck2so this is another side02:02
litghostI think keeping two copies is undesirable.  How much do you think you would need to keep aside?02:37
duck2i plan to translate the whole file to something like the flatbuffers schema. i think it will occupy ~1/3 of the xml file size in memory. maybe a far estimate?02:53
litghostOkay02:53
duck2(just realized xc7's rr_graph.xml gzips to 52mb)02:54
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litghostFYI, the flatbuffer version of the xc7 graph was ~150 MB uncompressed03:35
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sf-slack1<mkurc> Update on tile grid split: I'm still struggling to make the PicoSoC work. I've just discovered that for the PicoSoC I'm getting duplicated statements in `fasm` file. This is very wrong.08:58
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sf-slack1<mkurc> I've also discovered that `fasm` files generated even without my modifications also contain some statement duplicates. Is it an intended behavior ?10:04
sf-slack1<tmichalak> @mkurc: what happens at the next stage? what does fasm2frames say about this input? I would expect it to fail if such input was considered an error.10:12
sf-slack1<mkurc> The fasm2frames passes correctly. It does not consider this an error. Therefore I'm curious whether the fasm file can have duplicated statements.10:18
sf-slack1<tmichalak> Then I guess the duplicate entry is simply ignored. The question to ask here then is whether the entry that turned out to be a duplicate should be in fact a different feature, i.e. the prefix identifier might be incorrect10:29
sf-slack1<tmichalak> The xc7frames2bit tool is pretty much ready (https://github.com/SymbiFlow/prjxray/pull/705) and I was wondering what would be the best next step11:40
tpbTitle: Implement the xc7frames2bit tool by tmichalak · Pull Request #705 · SymbiFlow/prjxray · GitHub (at github.com)11:40
sf-slack1<tmichalak> In https://github.com/SymbiFlow/symbiflow-arch-defs/issues/418 one of the tasks says: "Modify harness generation to output all bits outside of ROI and add them to "required_features" in the design.json" maybe I could take care of that?11:41
tpbTitle: Remove use of design.bit (ROI bitstream harness) · Issue #418 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)11:41
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sf-slack1<acomodi> slicem and modes fix update: with this commit I have been able to add the test on the `Differing modes` issue. https://github.com/SymbiFlow/vtr-verilog-to-routing/pull/29/commits/8dfae8f4a387e3792dab427784a0a12f8aa4bf9414:16
tpbTitle: Differing modes between lib_nets fix by acomodi · Pull Request #29 · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com)14:16
sf-slack1<acomodi> I have tested that, without the slicem fix the regression test fails, while, by using the fixed VPR version the issue is correctly solved14:17
sf-slack1<acomodi> The only thing is that I have been able to isolate the `SLICEM` pb_type and it is more than 2000 lines long. I could try to further reduce it to have something more comprehensible, but I think this is a good starting point14:18
litghostmkurc: Duplicated FASM statements are expected and allowed.15:02
sf-slack1<mkurc> @litghost Ok, thanks15:03
litghosttmichalak: Sure15:07
litghostacomodi: First thing I would try is to simplify the FF tree, for example try getting rid of the 5FF's15:08
litghostacomodi: Might also see if you can safely remove the F8MUX and if yes, the F7MUX's15:09
sf-slack1<acomodi> litghost: All right15:12
sf-slack1<mkurc> @litghost: I am still fighting with implementation of the PicoSoC using the split grid. It is not working on the hardware. Neither does the Murax. However, simpler designs do work fine (eg. UART taken from the PicoSoC which continuously sends content of an initialized BRAM).15:14
litghostmkurc: Interesting.  Are you using the slower clock speed harness?15:15
sf-slack1<mkurc> I am running out of ideas what can be wrong. I am pretty sure that I've ruled out incorrect connection definitions.15:15
sf-slack1<mkurc> I tried slowing the PicoSoC down to 12.5 MHz. I can try slowing down even further.15:15
sf-slack1<mkurc> I am using the same harness and the clock division is implemented on logic (toggling FFs)15:16
litghostmkurc: Interesting.  I'm actively working on the FASM to Verilog converter.  It still needs testing and BRAM support, but that will enable use to check the picosoc bitstream in simulation.  I'm aiming to have BRAM support this week.  In order for the FASM to Verilog converter to work, I do need to fix https://github.com/SymbiFlow/prjxray/pull/727 to work on K7 and Z7.15:17
tpbTitle: Solve remaining bits in the ROI by litghost · Pull Request #727 · SymbiFlow/prjxray · GitHub (at github.com)15:17
sf-slack1<mkurc> Having FASM to verilog would be great15:18
sf-slack1<mkurc> @litghost: Actually, I have a question whether I am doing the connection definition correctly.15:26
sf-slack1<mkurc> Here is what I did: I split the CLB (with sites SLICE_X0 and SLICE_X1) to CLB_SLICE_X0 (with one site SLICE_X0) and CLB_SLICE_X1 (with one site SLICE_X1).15:26
sf-slack1<mkurc> For each new tile type I left only pips related to its site and removed the others. So the pips are split among new tile types.15:27
sf-slack1<mkurc> But I left all tile wires so they can serve as a pass-trhough connection when reaching from eg. INT_L through CLB_SLICE_X0 to CLB_SLICE_X1.15:27
sf-slack1<mkurc> And the problem is that the CLB_SLICE_X1 now contains the same wires as CLB_SLICE_X0. But wires related to SLICE_X0 in CLB_SLICE_X1 are not connected to any site within it.15:27
sf-slack1<mkurc> Can it cause any problems ?15:27
litghostmkurc: Depends. Have you pushed your latest PR?15:28
sf-slack1<mkurc> I need to check, but I think yes15:29
sf-slack1<mkurc> Yep, its there: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/43515:30
tpbTitle: WIP - Xilinx Series 7 split CLB tiles into two tiles types (SLICEL / SLICEM) by mkurc-ant · Pull Request #435 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)15:30
sf-slack1<mkurc> I think I will prepare some drawings which show the situation.15:31
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litghostmkurc: How are you testing the new tileconn.json?15:34
sf-slack1<mkurc> By feeding it through `prxray_` scripts.15:35
sf-slack1<mkurc> And using it to do the P&R.15:35
sf-slack1<mkurc> Also I've made a few crude utility scripts that allows me to render a section of the FPGA grid with connections to a SVG file.15:36
litghostmkurc: That's not testing.  You should write a test that ensures that the nodes from your tileconn.json are the same nodes as before.15:40
litghostmkurc: tileconn.json as a file format is a tricky thing, small changes can have big effects.  You need to ensure formally the the nodes from both tileconn.json are the same.15:41
sf-slack1<mkurc> You mean in the final routing graph ?15:41
litghostmkurc: Sort of.  You need to be sure that all sink instances connect to the same source instances.  When tileconn.json is first formed, this is done be comparing that all nodes (groups of wires) remain the same.15:43
litghostmkurc: You can't do the check that simply, because you have split the wires.15:43
litghostmkurc: But you can verify that every sink is connected to the correct sources15:43
sf-slack1<mkurc> Mhm15:44
mithrohttps://usercontent.irccloud-cdn.com/file/hKnWwcSO/image.png15:57
sf-slack1<mkurc> Tile grid split illustration: https://pasteboard.co/I6a5iCL.png16:02
tpbTitle: Pasteboard - Uploaded Image (at pasteboard.co)16:02
litghostmithro: ?16:05
mithroDiagram comparing Xilinx Slices to Intel ALMs I found in a paper I was reading earlier16:06
litghostAh16:12
mithroelms: https://docs.google.com/document/d/1Pd_ygB0PvSq_gPEYIm8sJEF-mYY2nk3kLsazLVL21uw/edit16:48
tpbTitle: VtR Python API Design Doc - Google Docs (at docs.google.com)16:48
elmsmithro: this is the doc used when developing lib/rr_graph  graph.py and channel.py?16:53
mithroelms: No, this is a doc to try and unify symbiflow and prga and provide an overall Python API for vtr xml generation16:54
elmsprga?16:55
mithrohttps://prga.readthedocs.io/en/latest/16:55
tpbTitle: Welcome to the documentation of Princeton Reconfigurable Gate Array! Princeton Reconfigurable Gate Array 0.1 alpha documentation (at prga.readthedocs.io)16:55
elmsFor anyone with thoughts on including hardware testing in our CI please discuss here: https://github.com/SymbiFlow/ideas/issues/2516:57
tpbTitle: Testing on hardware · Issue #25 · SymbiFlow/ideas · GitHub (at github.com)16:57
mithrolitghost: Should I be regenerating the database with your new ROI changes?17:01
litghostmithro: Not yet, need to get https://github.com/SymbiFlow/prjxray/pull/727 merges17:01
tpbTitle: Solve remaining bits in the ROI by litghost · Pull Request #727 · SymbiFlow/prjxray · GitHub (at github.com)17:01
mithrolitghost: Well, there is new ppips files already, right?17:01
litghostmithro: Those are of limited value without https://github.com/SymbiFlow/prjxray/pull/72717:02
tpbTitle: Solve remaining bits in the ROI by litghost · Pull Request #727 · SymbiFlow/prjxray · GitHub (at github.com)17:02
mithrolitghost: Just incase you didn't see -> https://github.com/YosysHQ/yosys/commit/8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b520:11
tpbTitle: Merge pull request #885 from YosysHQ/clifford/fix873 · YosysHQ/[email protected] · GitHub (at github.com)20:11
mithrolitghost: Linked from https://github.com/YosysHQ/yosys/issues/87320:11
tpbTitle: Regression when initial-ising reg used on negedge clock · Issue #873 · YosysHQ/yosys · GitHub (at github.com)20:11
litghostYa, I saw that20:11
litghostOpps20:11
litghostMakes sense when you see the fix20:12
mithrolitghost: Guess there should probably be some type of testing for it?20:12
litghostmithro: On the yosys side or our side?20:12
litghostmithro: FYI, we don't support negative clocks yet, so we can't test for it yet20:13
mithrolitghost: Probably on the yosys side?20:13
litghostmkurc: In doing the fasm 2 verilog I may have located a bug in the way we emit the routing graph.  Can you check for the following condition:20:26
litghostFAN_ALT[0-7] and BYP_ALT[0-7] that is being routed to both FAN[0-7]/BYP[0-7] and FAN_BOUNCE[0-7]/BYP_BOUNCE[0-7]20:26
litghostmkurc: I think the FAN_ALT and BYP_ALT output pips may be mutially exclusive, but no bit indicates this behavior20:26
litghostmkurc: If my theory is true, then the routing graph could enable an invalid configuration20:26
litghostmkurc: Never mind, the routing implementation is correct, must be a bug in fasm 2 verilog21:10
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litghostmkurc: I've tested https://github.com/SymbiFlow/symbiflow-arch-defs/pull/473 on some designs out of both Vivado and VPR.  It seems to be working, with differing routing.  I haven't added the TCL statements to apply the existing routing23:41
tpbTitle: WIP: Initial 7-series FASM to verilog conversion by litghost · Pull Request #473 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)23:41

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