Tuesday, 2019-03-12

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mithrolitghost: What is the ratio between edges and nodes that you have seen?00:13
litghostmithro: Right now 1:500:13
litghostmithro: But it varies00:13
mithrolitghost: Do you have a simple example with rr_graph metadata?00:39
litghostmithro: Like an XML?00:40
mithrolitghost: yeah00:40
mithrolitghost: Have you seen this structure before?01:40
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)01:40
mithroHadn't seen `map(EmployeeRecord._make, cursor.fetchall())` before...01:41
litghostmithro: Ya, but it would be of very limited value.  The amount of ORM'ing in the xc7 import is very small01:41
litghostmithro: Most of the SQL is purely relational01:41
mithrolitghost: you mentioned that just generation of the tuples / named tuples was taking significant time?01:42
litghostmithro: Ya, but the solution was to just skip generating the named tuple at all01:42
mithrolitghost: Should the  artix7/mask_clk_hrow_bot_r.db  still exist?01:50
mithrolitghost: It's not being generated...02:08
mithrolitghost: The patch file looked strange :-P -> https://github.com/SymbiFlow/prjxray/pull/71002:43
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sf-slack1<mkurc> The most up-to-date Yosys on Symbiflow repo does not infer BRAM (or other type of memory) correctly. It should do when defining an array in verilog and initializing it using `initial` statemets. I've created an issue: https://github.com/SymbiFlow/yosys/issues/1713:45
tpbTitle: Yosys cannot infer BRAM correctly on current master+wip · Issue #17 · SymbiFlow/yosys · GitHub (at github.com)13:45
sxperthave something related, Warning: Replacing memory \hex with list of registers. See saturn_debugger.v:15213:47
sxperthex is an array of bytes, should be a couple of 16x4 distributed rams13:48
daveshahmkurc: Does it work if you revert https://github.com/YosysHQ/yosys/pull/843/commits/7cfae2c52fb8e210a68032a109646785e4353dcc ?14:06
tpbTitle: Use mem2reg on memories that only have constant-index write ports by cliffordwolf · Pull Request #843 · YosysHQ/yosys · GitHub (at github.com)14:06
daveshahsxpert: in any case, a ROM will never be mapped to distributed RAM, as it is more efficient just to use LUTs14:07
daveshahsxpert: although I think it triggers this bug too, your case will always end up as LUTs14:07
sf-slack1<mkurc> Yeah, I've stumbled upon the problem while trying to place program memory for Picosoc in BRAM. I always ended up with it in LUTs.14:09
sf-slack1<mkurc> I'll check that commit14:09
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sf-slack1<mkurc> @sxpert You are right. The PR #843 to YosysHQ changes the behavior and the memory is no longer inferred when it is a ROM.14:18
daveshahProbably best if you create a GitHub issue upstream with your testcase14:20
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sf-slack1<mkurc> @daveshah https://github.com/YosysHQ/yosys/issues/86715:40
daveshahseems to be 404?15:41
sxpertsame here15:41
sxpertjust appeared15:43
sxpertbut only in the issue list15:43
daveshahWorking for me now15:43
sf-slack1<mkurc> Posted the file again in a comment15:43
sxpertah there15:44
sxpertguess it takes some time to replicate within github's infrastructure15:44
daveshahmkurc: if you are curious, the main purpose of #843 was to fix cases where an array was being used as an array of signals rather than a memory, rather than as an optimisation per se15:44
daveshahI think the solution will be to not apply it where the constant writes are in an initial15:44
sf-slack1<mkurc> Ok, I see.15:49
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mithro@mkurc: Did my comment on vtr #17 make sense?16:52
sf-slack1<mkurc> @mithro Yes, it does.16:53
mithromkurc: So the two things should be implemented without interacting with each other16:53
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sf-slack1<mkurc> Right, now it is clear for me16:54
mithroThe pip fuzzers seem to have been really flaky lately?16:56
mithrolitghost: The .patch file seems to be working okay!17:01
mithrolitghost: https://console.cloud.google.com/storage/browser/symbiflow-prjxray/artifacts/prod/foss-fpga-tools/prjxray/presubmit/database/zynq7/161/20190311-211723/database/17:01
tpbTitle: Google Cloud Platform (at console.cloud.google.com)17:01
mithrokgugala: Take a look at https://vtr-verilog-to-routing.readthedocs.io/en/latest/tutorials/timing_simulation/index.html17:22
tpbTitle: Post-Implementation Timing Simulation Verilog-to-Routing 8.0.0-dev documentation (at vtr-verilog-to-routing.readthedocs.io)17:22
mithroacomodi: https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/47817:24
tpbTitle: WIP: Replicate fan out issue by litghost · Pull Request #478 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)17:24
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duck2hello, now i hold ownership of one a7-35t17:57
duck2as far as i understand, currently i cannot go from verilog-->yosys->vtr->prjxray-->this device, right? vivado has to step in somewhere17:58
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litghostduck2: No, prjxray-db has the required inputs (which do currently come from vivado)18:05
litghostduck2: Assuming you are using a basys3.  If you want different pins or a different layout, then yes, Vivado is required.18:05
duck2what i have is a smaller thing called cmod a7. maybe stupid question but where do pin assignments come into play in the flow? in vtr arch def?18:13
litghostduck2: Okay, if you have different board you will need a new "harness", which does required vivado.18:14
litghostduck2: Harness generation is here: https://github.com/SymbiFlow/prjxray/tree/master/minitests/roi_harness18:15
tpbTitle: prjxray/minitests/roi_harness at master · SymbiFlow/prjxray · GitHub (at github.com)18:15
litghostduck2: Make a new file like this one https://github.com/SymbiFlow/prjxray/blob/master/minitests/roi_harness/basys3.sh18:15
tpbTitle: prjxray/basys3.sh at master · SymbiFlow/prjxray · GitHub (at github.com)18:15
litghostduck2: And add a case in https://github.com/SymbiFlow/prjxray/blob/master/minitests/roi_harness/runme.tcl#L15318:15
tpbTitle: prjxray/runme.tcl at master · SymbiFlow/prjxray · GitHub (at github.com)18:15
litghostduck2: FYI, we are relatively close to no longer needing the ROI harness, maybe 1 or 2 months?18:16
litghostduck2: If you are interested in helping with removing the need for the ROI harness, I can point you at issues required to remove the harness.18:16
duck2i think i saw the issues while exploring but had a hard time understanding why is a harness needed18:20
duck2is it so we generate the bitstream for the part we know about and place it inside a "general" bitstream generated by vivado?18:20
litghostduck2: Two reasons, IOBs and CLK trees18:21
litghostduck2: We are missing some segbits for CLKs, are missing synthesis of both IOBs and CLK trees, and do not have place and route support for IOBs and CLK trees18:21
litghostduck2: The ROI harness handles these things18:21
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litghostduck2: We are not missing many segbits for CLKs, roughly the 9 or so bits identified in https://github.com/SymbiFlow/prjxray/issues/68418:22
tpbTitle: Document all bits used in the basys3 SWBUT ROI · Issue #684 · SymbiFlow/prjxray · GitHub (at github.com)18:22
litghostduck2: Once those bits are documented, then arch defs for the IOB and CLK tree types need to be written, along with a sythesis step18:23
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duck2 i see. i would like to help, but i think first i should install vivado(had ise before) and try to make a harness for this device18:29
duck2so that i have a better grasp of things18:29
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duck2thx for the information^^18:30
litghostduck2: Sure.  I agree that having a harness is a good first step18:30
litghostFYI, you must use Vivado 2017.218:32
duck2ok. is the webpack sufficient or do i need a full license?18:33
litghostwebpack is fine18:39
mithrolitghost: https://github.com/SymbiFlow/prjxray/pull/715 <- that should fix my issue with the hclk bits missing?18:48
tpbTitle: Fix 048 not using correct directory. by litghost · Pull Request #715 · SymbiFlow/prjxray · GitHub (at github.com)18:48
litghostmithro: On a7, yes18:48
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mithrolitghost: https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/utils/prjxray_create_edges.py is the code which creates the edges, right?21:15
tpbTitle: symbiflow-arch-defs/prjxray_create_edges.py at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)21:15
litghostmithro: Yes21:15
mithrolitghost: It's zynq not zync :-P21:22
sxpertzinc ?21:27
mithrolitghost: Do you have a doc which explains the dataflow with the new sqlite process? It seems like you generate the edges into the `graph_edge` table?21:59
litghostmithro: You mean https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/utils/lib/connection_database.py#L1622:00
tpbTitle: symbiflow-arch-defs/connection_database.py at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)22:00
mithrolitghost: Building channels is then done as part of the "mark_track_liveness"?22:00
litghostmithro: We only need channel ptc's for live channels22:01
mithroLive means a track which has a connection to another track?22:01
litghostmithro: Liveness should mean that it is possible to route on it22:02
litghostmithro: Liveness is mostly a ROI based concept22:02
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