Friday, 2019-03-08

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mithroLooks like we currently need a zybo harness in prjxray-db ?00:29
litghostmithro: I actually thought we already had one.00:39
litghostmithro: I'd hate to gate merging a patch because we don't have autoformatting00:39
mithroNo harness directory in https://github.com/SymbiFlow/prjxray-db/tree/master/zynq700:39
tpbTitle: prjxray-db/zynq7 at master · SymbiFlow/prjxray-db · GitHub (at github.com)00:39
litghostmithro: Ya, I saw that too00:40
mithrolitghost: Doing that now00:40
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mithro(Generating the harness that is)00:40
litghostright00:41
litghostYou might need to shrink the harness away from the IOB tiles00:41
litghostBut try it and see if the harness still generates00:41
mithrohttps://github.com/SymbiFlow/prjxray/issues/70300:44
tpbTitle: Building roi_harness for zybo fails · Issue #703 · SymbiFlow/prjxray · GitHub (at github.com)00:44
litghostYa, move the grid away from the IOB's00:46
litghostNvm, that isn't the issue00:46
litghostAre you generating the harness with the zync db populated?00:47
mithroI did it with whatever is the latest content in the published db00:47
litghostWhich unknown bit is in that base address?00:47
litghostAh00:48
litghostAny change the BUFG drivers are in the ROI?00:48
litghostOr the near the ROI, like 1 or 2 columns?00:48
litghostchance*00:48
litghostBecause that error is saying that the ROI address range contains some unknown features, and in some cases symbiflow might zero them00:49
litghostThat address range corrisponds with the clock column00:49
litghostJust double checked tilegrid, that base address does not contain a BUFG00:50
litghostSo there must be a bit in either the BUFG_REBUF or CLK_HROW_TOP_R we don't understand00:51
litghostmithro: Attach the design.fasm or copy/paste the unknown features00:52
litghostTo https://github.com/SymbiFlow/prjxray/issues/70300:52
tpbTitle: Building roi_harness for zybo fails · Issue #703 · SymbiFlow/prjxray · GitHub (at github.com)00:52
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mithrolitghost: Attached01:06
mithrolitghost: Took me a while to figure out how to copy the file to a computer I could upload on and then figure out a file format github would accept01:08
litghostmithro: Opps01:08
mithrolitghost: Do you know if the "WARNING: [Vivado 12-3286] Net, clk, could not be marked fixed.  The net is either fully contained within a site or is unrouted." are normal?01:12
litghostI do not know01:12
mithrolitghost: I have discovered an issue in the way I'm doing the Info.md -- it is hard to tell when the zynq db was last updated....01:15
litghostmithro: I'm pretty certain it isn't an old DB.  The relevant bit is just missing, meaning a problem with the fuzzer01:15
mithrolitghost: Looks like I get that warning with the artix7 harness too01:16
mithrolitghost: I think I just fail at using github...01:23
mithrolitghost: Looks like there are no CLK_HROW_CK_IN_L5 lines in the zynq7 at all...01:25
litghostI noticed that too01:26
litghostLike I said, probably a fuzzer bug.01:26
litghostI think I disabled the IN_L5 fuzzing on zync because there were no MMCM or PLL's on that side of the chip, which was how I was fuzzing the L side pips.  If we need the L side pips, then we'll have to use IOB's on the left side01:27
litghostwhich is annoying01:27
litghostYa, I disabled the L side pips in https://github.com/SymbiFlow/prjxray/commit/bd42b809a4bd205814366f089dca33864cfc5c1601:32
tpbTitle: Limit target pips on zync to avoid unsolvable bits. · SymbiFlow/[email protected] · GitHub (at github.com)01:32
litghostMaybe that was a mistake01:32
mithrolitghost: btw it looks like you always mispell zynq as zync :-P01:34
mithrolitghost: Removing that filter and the fuzzer still seems to run?01:37
mithrolitghost: Doesn't look like it solves any more bits however...01:41
mithrolitghost: How did you generate the "# In frame 0x0000139a 3 bits were not converted." bit?02:11
mithrolitghost: Adding the bits from the artix7 into zynq7 doesn't seem to solve the missing bits in the design02:39
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mithrokgugala / acomodi: What is the status of stuff on zynq? It seems I can't generate a harness at the moment?16:27
mithrohttps://github.com/SymbiFlow/prjxray/issues/70316:31
tpbTitle: Building roi_harness for zybo fails · Issue #703 · SymbiFlow/prjxray · GitHub (at github.com)16:31
sf-slack1<acomodi> Hi mithro: we are still working on the ROI harness minitest for the zynq that will enable UART through a PMOD and the leds16:40
sf-slack1<acomodi> litghost: quick question about DRAMS: if a SLICEM is in DRAM mode some of its LUTs (except for LUTD) can operate in LUT mode right? This because I have seen that when using SLICEMs for carry chain, they do operate in `DRAMs` mode, but all the LUTs in SLICEM operate in `LUT` mode and none of them is actually a DRAM. I tried to remove the `LUT` mode from `ntemplate.N_dram.pb_type.xml` and SLICEM's were correctly17:26
sf-slack1packed. This is not the solution, but at least I am sure of what is happening there now.17:26
litghostacomodi: Correct.  It appears the only requirement the hardware imposses is if any DRAM, D-LUT must be in RAM mode.  Other 3 can be in any mode.17:29
sf-slack1<kgugala> initial BEL timing fuzzer https://github.com/SymbiFlow/prjxray/pull/70617:49
tpbTitle: WIP: fuzzers: timings: add bel timing fuzzer by kgugala · Pull Request #706 · SymbiFlow/prjxray · GitHub (at github.com)17:49
litghostmithro: I've formatted the SQL queries in https://github.com/SymbiFlow/symbiflow-arch-defs/pull/44518:45
tpbTitle: Initial SQLite3 XC7 routing graph implementation. by litghost · Pull Request #445 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)18:45
mithrolitghost: 3,632,632 kB == 3.6 gigabytes?22:03
mithrolitghost: IE you might want to use better units :-P22:03
litghostmithro: Ya, GB.  That is the output from /usr/bin/time, not the best units.23:27

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