Tuesday, 2019-03-05

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mithrolitghost: The python module for talking to the Make jobserver I was working on is here -> https://github.com/mithro/python-make-jobserver00:16
tpbTitle: GitHub - mithro/python-make-jobserver: Library for integrating Python applications with Makes jobserver. (at github.com)00:16
Bertl_oO'make env' fails with:00:26
Bertl_oOCommand "/fast/FPGA/PRJXRAY/prjxray.git/env/bin/python3 -c "import setuptools, tokenize;__file__='/tmp/pip-build-57v4z0_7/scipy/setup.py';exec(compile(getattr(tokenize, 'open', open)(__file__).read().replace('\r\n', '\n'), __file__, 'exec'))" install --record /tmp/pip-j0vyaa6v-record/install-record.txt --single-version-externally-managed --compile --install-headers /fast/FPGA/PRJXRAY/prjxray.git/env/include/site/python3.5/scipy" failed with error code00:26
Bertl_oOany suggestions how to make that work?00:27
litghostI would start by pasting the error properly formatted into a pastebin or equiv00:28
litghostBertl_oO: https://github.com/numpy/numpy/issues/8697 , Google is your friend00:34
tpbTitle: import numpy error: undefined symbol: zgelsd_ · Issue #8697 · numpy/numpy · GitHub (at github.com)00:34
Bertl_oOnot sure what that should tell me though00:36
Bertl_oOthis is an error on the build in the virtenv, no?00:37
Bertl_oOdo I need to install special version of numpy? if so, which one?00:43
mithroBertl_oO: "The catch is that both atlas and lapack provide liblapack.so.3. I assume from the naming that lapack is the canonical one and the one in atlas is intended to be an optimized one or something. The two are incompatible at the moment which is where the problem arises."00:45
Bertl_oOso get rid of atlas should help?00:47
mithroBertl_oO: Dunno - but it seems like it is something to do with your system and atlas / lapack00:48
Bertl_oOhow do I rerun the 'make env' so that it tries again?00:48
Bertl_oOi.e. how do I undo 'make env'?00:49
mithroBertl_oO: "rm -rf env" ?00:49
elmsBertl_oO: are you on step 5 and taking option 1 I assume?00:49
elms`make env -B` should work too00:49
mithroBertl_oO: https://github.com/SymbiFlow/prjxray/blob/acf7aafce16a7f37e248e1403d8ef01b250116d0/Makefile#L3-L2000:49
tpbTitle: prjxray/Makefile at acf7aafce16a7f37e248e1403d8ef01b250116d0 · SymbiFlow/prjxray · GitHub (at github.com)00:50
Bertl_oOelms: yep, step 5, option 100:50
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Bertl_oOfor the record, removing atlas seems to have done the trick01:03
Bertl_oOstill a bunch of 'Errors' on the way but it seems to have finished now01:04
Bertl_oOmoving on to step 7, option 201:04
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tpbTitle: Support for shorthand to specify all pins on one edge · Issue #475 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)02:24
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Bertlhmm ... the xc7z020clg400 database build is still ongoing ... but I'm curious, how can I use the database (once it finishes) to figure out the frame address/location/mask from a given tile?13:53
sf-slack<kgugala> hi Bertl13:55
sf-slack<kgugala> you can check the tilegrid.json file within the db13:56
Bertlyeah, I'm looking at that right now13:56
Bertlbut it only contains grid coordinates?13:56
Bertl(looking at the xc7z010clg400-1 for now)13:57
sf-slack<kgugala> you can find there baseaddreses13:57
sf-slack<kgugala> in bits sections13:57
sf-slack<kgugala> (not every tile has it filled)13:57
Bertlah, I see, didn't scroll down far enough13:58
sf-slack<kgugala> :slightly_smiling_face:13:58
Bertlso, for example, CLBLL_L_X16Y93 has an entry in the bits section13:59
Bertlit says CLB_IO_CLK (what does that mean?)14:00
Bertland it reports two SLICEL sites (which looks like what I'm looking for)14:00
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Bertlwhat does the 'frames: 36' mean?14:03
kgugalahow many frames there are in the bitstream for this type of column14:04
kgugalayou may want to check fuzzer 005-tilegrid14:05
kgugalathe json is generated by this fuzzer14:05
Bertlhmm, so what does 'offset: 40' in a context of 36 frames mean?14:09
Bertlthe offset in a frame or the offset to the given baseaddress?14:09
sf-slack<kgugala> check this https://prjxray.readthedocs.io/en/latest/format/tile.html#tilegrid-json14:11
tpbTitle: Introduction Project X-Ray documentation (at prjxray.readthedocs.io)14:11
BertlI guess the documentation is not up-to-date, but thanks for the link14:13
sf-slack<kgugala> yeah, it needs an update14:13
Bertlso most likely the 'offset' is the inter-frame offset originally in the same tuple as the baseaddr14:13
sf-slack<kgugala> but the json format descritption should be OK14:13
Bertlso this is what I see in the database: https://pastebin.com/raw/ry8RdQV614:14
BertlI presume the '99' from the docs corresponds to the 38 in the paste14:15
sf-slack<kgugala> yep14:16
Bertlso I would find the SLICE_X40Y19 and SLICE_X41Y19 config data at frame 0x00401A00, offset 38 and 3914:18
Bertlnow how do the 36 frames factor into this?14:19
Bertlah, the database build for the xc7z020clg400-1 just failed :(14:21
sf-slack<kgugala> on what?14:21
sf-slack<kgugala> on which fuzzer?14:22
sf-slack<kgugala> can you paste the log?14:22
Bertlis there a complete log generated somewhere?14:22
kgugalaeach fuzzer should have `log` folder14:24
kgugalainside you can find the full log14:24
Bertlthere are quite a number of files there, how to narrow it down to the relevant one(s)?14:25
kgugalagrep for erorrs?14:26
kgugalain stdout files you have all the output14:27
tpbTitle: Index of /Stuff/PRJXRAY/logs/ (at vserver.13thfloor.at)14:35
Bertlany idea what the problem could be?14:41
sf-slack<acomodi> What version of vivado are you using?14:42
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Bertlthe suggested 2017.214:42
sf-slack<acomodi> Ok, could you zip all the logs?14:52
Bertlof this particular fuzzer or of all fuzzers?14:52
sf-slack<acomodi> For now the 005 will be fine14:53
sf-slack<acomodi> https://pastebin.com/mvEM2aP615:04
tpbTitle: 0_sponge_log.xml:3820:OSError: [Errno 28] No space left on device 0_sponge_log. - Pastebin.com (at pastebin.com)15:04
sf-slack<acomodi> found this, could it be that your system run out of space?15:04
Bertlthat was yesterday15:04
Bertlmade more space on the partition and ran make again15:05
sf-slack<kgugala> so Bertl, can you provide the recent logs?15:05
Bertlthe zip contains all logs in the folder (as does the link)15:05
tpbTitle: Index of /Stuff/PRJXRAY/ (at vserver.13thfloor.at)15:05
Bertl# zip 005-tilegrid-logs.zip 005-tilegrid/logs15:06
sf-slack<kgugala> can you filter them to contain only the most recent ones?15:06
sf-slack<kgugala> the out of space error was in the logs15:06
Bertlclick on 'Last Modified' and they will be sorted according to the date15:06
sf-slack<kgugala> you have a bunch of critical warnings in the logs15:24
sf-slack<kgugala> I see you run it for 702015:24
sf-slack<kgugala> as @litghost said yestarday - the soft was not tested on this chip15:25
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sf-slack<kgugala> there is a bunch of critical warnings like:15:25
sf-slack<kgugala> Cannot loc instance 'idelay_IDELAY_X0Y2' at site IDELAY_X0Y2, Site IOB_X0Y2 is not bonded. Place terminal di[15] and connected instances in a site with a PAD15:25
Bertlso how to get the database for 7020? what needs to be modified?15:26
sf-slack<kgugala> also in `stdout.2019-03-05T12:38:38.534252.log` at line 8833 Vivado fails15:26
sf-slack<kgugala> to get the database you have to set the part as you did and run fuzzers15:26
Bertlnote: I'm only interested in the frame addresses for tiles, specifically slices15:27
sf-slack<kgugala> since they were not tested on 7020 they may fail15:27
sf-slack<kgugala> as they did15:27
Bertlhow to fix them?15:27
sf-slack<kgugala> you'd need to dive a little into the fuzzer code and check what exactly is happening there15:28
sf-slack<kgugala> I assume that tailoring the settings in settings.sh file for Zynq will be required to get the 7020 to work15:28
Bertlso it's a problem with the XRAY_ROI_* settings?15:30
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litghostBertl: Tile grid ignored ROI to map all the base addresses.  If you only care about slices, you can disable the IOB and IOB_INT tile fuzzers and file an issue.15:31
litghostBertl:  IDELAY's are only used by tilegrid when trying get addresses for IOB tiles and IOB INT tiles15:32
Bertlhow do I do that?15:32
litghostBertl: Comment it out from the 005 makefile depedencies15:32
litghostBertl: Comment line 4 and 5 https://github.com/SymbiFlow/prjxray/blob/master/fuzzers/005-tilegrid/Makefile#L415:33
tpbTitle: prjxray/Makefile at master · SymbiFlow/prjxray · GitHub (at github.com)15:33
Bertlokay, then just run make again?15:33
litghostBertl: Just run make in the 005 directory15:33
litghostOtherwise it will restart the fuzzer, which will take significantly longer15:34
litghostFor info on how the tilegrid and segbits are related, https://github.com/SymbiFlow/prjxray/blob/master/prjxray/tile_segbits.py15:34
tpbTitle: prjxray/tile_segbits.py at master · SymbiFlow/prjxray · GitHub (at github.com)15:34
litghostBertl: What are you interested in doing?15:35
BertlI'm interested in mapping specific (marked) slices to frame addresses so that they can be modified at runtime15:35
litghostBertl: Sure, then tilegrid and the CLB segbits are what you want15:36
litghostBertl: You will also likely want INT segbits, but the CLB and INT segbits appear to be common across all 7-series parts15:37
litghostBertl: Only tilegrid.json and tileconn.json are expected to be part specific15:38
sf-slack<kgugala> @Bertl you may also want to take a look on the xc7patch tool (in the tools folder)15:38
Bertllitghost: okay, tx15:38
Bertlkgugala: what does it do?15:38
sf-slack<kgugala> it can patch the bitstream in the selected region with a data from another bitstream15:39
Bertlah, got it, tx15:39
litghostThe circle flow is bit2fasm.py, fasm2frames.py and then xc7patch15:39
sf-slack<kgugala> you, after some modifications it can be helpful in your case15:39
sf-slack<kgugala> s/you/so15:40
Bertlyeah, might come handy for testing ...15:43
Bertllitghost: make failed with https://pastebin.com/raw/rM00W5mt15:48
sf-slack<kgugala> this is easy to fix15:48
sf-slack<kgugala> just change the assert condition15:49
sf-slack<kgugala> if you look at the code it will alway if the part is not 701015:49
Bertlassert os.getenv('XRAY_PART') in ("xc7z010clg400-1", "xc7z020clg400-1") ?15:50
litghostYes, that's good15:50
BertlI read in the docs that BRAM frame to memory is not currently understood ... is that still correct?16:09
litghostbertl: Incorrect.  We believe to have all BRAM bits understood16:10
litghostbertl: If you are interested in creating a BRAM patching tool, we have an outstanding issue to do just that!16:10
Bertlokay, because the assignment didn't seem that unusual/unexpected last time I checked16:11
tpbTitle: Create tool to patch blockram (BRAM) contents in bitstream · Issue #181 · SymbiFlow/prjxray · GitHub (at github.com)16:11
litghostSorry, I don't parse that16:11
Bertlframe address to memory locations16:11
Bertlthe correlation I mean16:11
litghost005 will output BRAM base addresses for BRAM configuration and BRAM data.  We have used the both to create designs that use BRAM's outside of vivado, so I have pretty good confidence that it is work16:12
Bertlexcellent, any documentation available on this?16:13
Bertlmost recent error: https://pastebin.com/raw/BzXyWEnK16:14
litghostThe most straight forward way to deal with BRAM data is via FASM directives and fasm2frames.py16:14
litghostThat error is very weird16:15
Bertlwell, there is no INT_L_X0Y50 in build/basicdb/tilegrid.json16:16
litghostYa, but then how did dsp_int output that!!!  dsp_int uses basicdb as well16:16
litghostRun "make clean" in the dsp_int folder and try again16:16
litghostAny chance you ran 005 with another part at some point16:17
Bertlnot that I can remember16:17
Bertlrerunning now (after clean)16:17
Bertlso, back to the BRAM ... the idea is to generate FASM input and then use fasm2frames.py and xc7patch to make the changes?16:26
litghostMost of the work is actually mapping pre-synthesis addresses to tiles, which is an open question.16:27
litghostSo if the BRAM is simple, e.g. one tile, then it is easy16:27
Bertlis there some FASM documentation available?16:27
tpbTitle: fasm/specification.rst at master · SymbiFlow/fasm · GitHub (at github.com)16:27
litghostFASM itself is a language for writing out features16:28
Bertlso for a BRAM tile, there would be a single line specifying the tile and the assigned data, yes?16:29
Bertl(a rather long line probably :)16:29
litghostIn the BRAM case, something like:16:30
litghostYou can split it up as needed16:30
Bertlah, so have a bunch of 'sub' ranges16:31
litghostso [63:0], [127:64], etc etc16:31
Bertlyeah, got it16:31
litghostEven that line is a 256 subrange16:31
litghostWe are currently using the INIT_xx syntax from the RAMB18E116:31
Bertlokay, does the data need to be binary?16:31
litghostbertl: Not sure I understand your question.  FASM supports an verilog integer constant16:32
Bertlah, no, I see, 'h should be fine as well16:32
Bertlso and the data generated by fasm2frames.py is what format?16:33
litghostfasm2frames.py is a frame words CSV, first column is frame address, followed by 101 32-bit words16:34
litghostxc7patch can read frame words CSV16:34
Bertlokay, makes sense16:35
Bertlwell, clean and make did result in the very same error16:41
BertlKeyError: 'INT_L_X0Y5016:41
BertlMakefile:108: recipe for target 'build/tilegrid_tdb.json' failed16:41
Bertlanything I should upload?16:43
litghostFile an issue with replication instructions.16:53
mithrokgugala: The image on https://symbiflow.github.io/ for GSoC is broken17:22
tpbTitle: SymbiFlow - the GCC of FPGAs (at symbiflow.github.io)17:22
Bertllitghost: hmm, I started from scratch and just focused on the 005-tilegrid17:30
Bertlfor some reason, vivado seems to be using the xc7a50t-fgg484 as part despite of the source settings/artix7.sh17:31
litghost ah, that would totally cause a problem17:31
Bertlah, sorry, I might have messed up17:31
Bertllet me recheck17:31
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Bertlokay, I messed up before but now the process is like this:18:11
Bertlit seems that the xc7z020clg400-1.yaml is missing, how do I generate that without running all the 8+ hours of fuzzer builds?18:12
litghostrun 00118:21
Bertlk, tx18:21
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Bertlhmm, didn't really help as it seems ... 005 still complains after running make in 00118:27
Bertlmaybe make pushdb ?18:27
litghostWhen running a fuzzer, you can do "make -j<N> run" and it will do the pushdb for you18:28
Bertlah, okay18:28
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litghostword of warning, "make run" does perform a "make clean", so partial results will be removed18:28
litghostwhich may or may not be what you want18:28
Bertlyeah, just saw it in the makefile18:29
sf-slack<mgielda> @mithro we know, we are in the process of fixing it18:43
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sf-slack<kgugala> @mithro https://github.com/SymbiFlow/symbiflow-website/pull/2519:56
tpbTitle: Add missing GSoC logo by kgugala · Pull Request #25 · SymbiFlow/symbiflow-website · GitHub (at github.com)19:56
tpbTitle: 005-tilegrid fails for Zynq 7020 · Issue #697 · SymbiFlow/prjxray · GitHub (at github.com)20:03
Bertlbtw, it seems the INT_L_X0Y50 is related to the fake ps7 entry20:17
litghostYou could try removing the ps7_int fuzzer too20:17
Bertlcould it be that just the location changed between 7010 and 7020?20:18
litghostComment out the dependency, same as iob20:18
Bertlbecause otherwise I think the ps7 is identical between 7010 and 702020:18
litghostthe ps7_int fuzzer likely needs to use the basicdb grid rather than hard coding a tile20:18
litghostAnyways, if you don't need INT base addresses near the PS7 block, you don't need to fix this20:19
Bertlokay, so sed -i '/TILEGRID.*ps7/ s/^/#/' Makefile20:20
Bertlbut I do not think that changes much20:21
BertlI'll just remove the entry from ../005-tilegrid/ps7_int/build/segbits_tilegrid.tdb for now20:29
Bertlwhich brings me to the next error:20:30
BertlAssertionError: BRKH_INT_PSS20:30
litghostThat isn't enough information20:39
litghostYou can likely add BRKH_INT_PSS to the assertion list.  That assertion is sanity checking the structure of the INT columns20:46
litghostIf you want to be sure, open up Vivado and see that there are no INT tiles "beyond" BRKH_INT_PSS20:47
tpbTitle: prjxray/generate_full.py at master · SymbiFlow/prjxray · GitHub (at github.com)20:47
Bertlwell, adding BRKH_INT_PSS to the assertion list results in a new KeyError20:49
litghostThat's a side affect of removing the IOB fuzzer20:57
Bertlany suggestion how to work around that?20:58
litghostRemove the call to propagate_IOB_SING20:58
Bertlgreat! that worked21:00
Bertlthanks for the help so far!21:01
Bertlso I have the tilegrid database now ... do I just take the segbit stuff from 7010?21:06
litghostYou can, it should work.  As far as we can tell, all the 7-series segbits are the same21:18
Bertlokay, anything else I need to build for the tools?21:19
Bertl(i.e. fasm2frames.py and xc7patch)21:19
litghostxc7patch is build via CMake21:20
litghostfasm2frames.py just needs a database and the prjxray python lib21:20
litghostbit2fasm.py needs a database and the tools built21:20
Bertllooks like I'm getting there :)21:22
Bertlwhat is the syntax of the segbits_* files?21:23
tpbTitle: prjxray/tile_segbits.py at master · SymbiFlow/prjxray · GitHub (at github.com)21:25
Bertlhmm, okay ... so what does 30_00 !30_01 30_02 !30_03 mean?21:31
elmsBertl: That's the bits to set and clear. So set bit 30_00 and 30_02 and clear 30_01 and 30_03 The tuple is a coordinate of a specific bit for that tile.21:43
Bertlokay, how does that map to the frame location?21:44
Bertllet's say I have SLICE_X28Y68 in tile CLBLL_L_X20Y6821:46
BertlI know the base address is 0x00400A00 and the offset is 3621:46
Bertlthe slice(s) cover two words there (accroding to the database)21:47
Bertlnow the segbits_clbll_l.db tells me that21:47
BertlCLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_0321:47
Bertlor let's make it simpler, for INIT[00] it tells me:21:48
BertlCLBLL_L.SLICEL_X0.ALUT.INIT[00] 32_1521:48
Bertlwhich means the 'bit' at coordinate (32,15)?21:48
elmsThat's my understanding, but I'm not familiar with the details of mapping with address and offset.22:07
Bertlokay, tx22:10

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