Friday, 2019-02-15

*** tpb has joined #symbiflow00:00
*** citypw has joined #symbiflow02:02
*** jevinskie has joined #symbiflow04:39
kgugalaMorning mithro08:51
*** acomodi has joined #symbiflow09:50
*** citypw has quit IRC09:59
mkurcI need some advice11:57
mkurcI am trying to migrate all VPR related stuff out of Yosys11:57
mkurcI want to have a common flow for Vivado and VPR up to some point:11:58
mkurcVerilog -> synthesis(yosys) -> edif -> Vivado11:59
mkurcand Verilog -> synthesis(yosys) -> techmap(in yosys) -> blif -> VPR11:59
mkurcThe problem is that i need to map $alu to a chain of CARRY4 which are understandable by Vivado11:59
mkurcand it works12:00
mkurcHowever, I cannot map CARRY4 to a chain of CARRY0 + 3xCARRY which are understandable by VPR12:00
mkurcCARRY0 and CARRY have separate output ports for carry chain and fabric12:00
mkurcand the Vivado's CARRY4 does not. It only has a "general" output. I guess that Vivado infers it later (after loading EDIF netlist) whether to connect it to fabric or carry chain.12:01
mkurcSo it seems that removing VPR stuff from Yosys completely is not possible.12:02
mkurcEither we will have some VPR stuff in Yosys or we implement inference of carry chain connections in VPR (right?)12:03
mkurcAlso the CARRY4 does not allow direct control of the chain intialization mux. It must also be inferred in Vivado12:05
*** jevinskie has quit IRC12:15
*** jevinskie has joined #symbiflow14:23
*** citypw has joined #symbiflow14:41
*** jevinskie has quit IRC15:26
*** simpleuser has joined #symbiflow15:54
mkurcI've confirmed that xc7/tests/counter does not work from latest master branch (4b66516). I've created a related issue on Github - #38216:36
*** jevinskie has joined #symbiflow16:38
*** jevinskie has quit IRC17:37
elmslitghost: I have a iCE40 fasm file Please comment on the gist with any feedback.19:14
tpbTitle: iCE40 FASM ยท GitHub (at
*** OmniMancer has joined #symbiflow23:54

Generated by 2.13.1 by Marius Gedminas - find it at!